EN 
Українська
Polski
Español
Deutsch
日本語
Italiano
Português (BR)
Français
العربية
Nederlands
中文
한국어
हिन्दी
Türkçe
Tiếng Việt
Русский
Bahasa Indonesia
فارسی
বাংলা
ไทย
Filipino
Kiswahili
اردو
Bahasa Melayu
தமிழ்
עברית
Ελληνικά
ਪੰਜਾਬੀ
አማርኛ
မြန်မာဘာသာ
ខ្មែរ
ქართული
नेपाली
Монгол хэл
Հայերեն
සිංහල
ລາວ
Čeština
Română
Magyar
Български
Svenska
Dansk
Suomi
Norsk
Slovenčina
Hrvatski
Српски
Slovenščina
Lietuvių
Latviešu
Eesti
Íslenska
Shqip
Македонски
Bosanski
Malti
Azərbaycanca
Қазақша
O'zbekcha
Тоҷикӣ
КыргызчаPhase-Locked Loop (PLL) — Clock Recovery & Carrier Sync
Interactive 3D phase-locked loop: Blender oscilloscope, signal generator and PLL board with phase detector, loop filter and VCO; second-order loop wn and zeta, lock range, cycle slips, noise bandwidth and in-page numerical checks.
🔁 Phase-Locked Loop (PLL)
A PLL is a feedback control system that makes one oscillator lock its phase and frequency to another. From FM radio demodulators to CPU clock generators, PLLs are one of the most widely used circuits in electronics.
What It Demonstrates
A 2nd-order PLL has three blocks: (1) a Phase Detector that produces a voltage proportional to the phase difference between input and VCO, (2) a Loop Filter that shapes the feedback — a PI (proportional-integral) filter gives zero steady-state phase error, (3) a VCO whose frequency shifts proportionally to its input voltage. The loop dynamics are governed by two parameters: natural frequency ωn (how fast it locks) and damping ratio ζ (how oscillatory the transient is). For ζ = 0.707 (a common design choice) the loop settles quickly without ringing. For ζ < 0.5 the phase error overshoots and rings before settling.
Did You Know?
Every modern processor uses a PLL to multiply a low-frequency reference clock (e.g. 100 MHz crystal) up to GHz speeds (3–5 GHz). GPS receivers use a PLL to lock onto each satellite carrier (1575.42 MHz for L1). The invention of the PLL is credited to Henri de Bellescize, who described it in a 1932 French paper on homodyne reception.
About this simulation
Frequently asked questions
What do damping ratio ζ and natural frequency ωn actually control?
Together ζ and ωn set the loop's second-order response, the same way they would for a mechanical spring-mass-damper system. Natural frequency ωn sets how fast the loop reacts — a higher ωn locks faster but tracks more of the input noise. Damping ratio ζ sets how oscillatory the transient is: ζ = 0.707 gives a quick, near-optimal response with minimal overshoot, ζ well below 0.5 produces visible ringing in the phase-error plot before it settles, and ζ above 1 gives a sluggish, overdamped approach to lock.
Where are phase-locked loops used in real electronics?
PLLs are one of the most common building blocks in electronics. Clock generation and frequency synthesis circuits use a PLL to multiply a stable low-frequency crystal reference up to the multi-gigahertz clock speeds modern processors need. Digital receivers use PLL-based clock and data recovery (CDR) circuits to re-derive a clean bit clock from a noisy incoming data stream. FM radio demodulators use a PLL to track the carrier's instantaneous phase and recover the audio signal, and GPS receivers use PLLs to lock onto each satellite's carrier frequency for precise ranging.
🔁 Phase-Locked Loop (PLL)
A PLL is a feedback control system that makes one oscillator lock its phase and frequency to another. From FM radio demodulators to CPU clock generators, PLLs are one of the most widely used circuits in electronics.
What It Demonstrates
A 2nd-order PLL has three blocks: (1) a Phase Detector that produces a voltage proportional to the phase difference between input and VCO, (2) a Loop Filter that shapes the feedback — a PI (proportional-integral) filter gives zero steady-state phase error, (3) a VCO whose frequency shifts proportionally to its input voltage. The loop dynamics are governed by two parameters: natural frequency ωn (how fast it locks) and damping ratio ζ (how oscillatory the transient is). For ζ = 0.707 (a common design choice) the loop settles quickly without ringing. For ζ < 0.5 the phase error overshoots and rings before settling.
Did You Know?
Every modern processor uses a PLL to multiply a low-frequency reference clock (e.g. 100 MHz crystal) up to GHz speeds (3–5 GHz). GPS receivers use a PLL to lock onto each satellite carrier (1575.42 MHz for L1). The invention of the PLL is credited to Henri de Bellescize, who described it in a 1932 French paper on homodyne reception.
About this simulation
Frequently asked questions
What do damping ratio ζ and natural frequency ωn actually control?
Together ζ and ωn set the loop's second-order response, the same way they would for a mechanical spring-mass-damper system. Natural frequency ωn sets how fast the loop reacts — a higher ωn locks faster but tracks more of the input noise. Damping ratio ζ sets how oscillatory the transient is: ζ = 0.707 gives a quick, near-optimal response with minimal overshoot, ζ well below 0.5 produces visible ringing in the phase-error plot before it settles, and ζ above 1 gives a sluggish, overdamped approach to lock.
Where are phase-locked loops used in real electronics?
PLLs are one of the most common building blocks in electronics. Clock generation and frequency synthesis circuits use a PLL to multiply a stable low-frequency crystal reference up to the multi-gigahertz clock speeds modern processors need. Digital receivers use PLL-based clock and data recovery (CDR) circuits to re-derive a clean bit clock from a noisy incoming data stream. FM radio demodulators use a PLL to track the carrier's instantaneous phase and recover the audio signal, and GPS receivers use PLLs to lock onto each satellite's carrier frequency for precise ranging.
Interactive 3D phase-locked loop: Blender oscilloscope, signal generator and PLL board with phase detector, loop filter and VCO; second-order wn and zeta, lock range, cycle slips and noise bandwidth with in-page numerical checks.
3D · Three.js / WebGL renderer · 60 FPS target · runs fully client-side, no install