Phase-Locked Loop (PLL) | mysimulator.uk

Three blocks in a loop

A phase-locked loop is a feedback control system built from three blocks in a ring: a phase detector (PD) that compares the phase of an incoming reference signal against the loop's own output, a loop filter that smooths that comparison into a slowly varying control voltage, and a voltage-controlled oscillator (VCO) whose output frequency is set by that voltage and is fed back to the phase detector, closing the loop.

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The mechanism is a simple negative feedback argument. If the VCO's phase lags the reference, the phase detector's error signal pushes the loop filter's output up, which speeds the VCO up, which reduces the lag; if the VCO leads, the opposite correction slows it down. At lock, the loop has driven the phase error to a small, stable value (often exactly zero for an ideal integrating loop filter) and, critically, the VCO's frequency exactly tracks the reference's frequency — a PLL is fundamentally a frequency-tracking device that achieves that tracking by continuously correcting phase.

Loop filter, damping and the trade-off it controls

The loop filter is almost always more than a simple low-pass — a proportional-plus-integral filter is standard, because the integral term is what lets the loop track frequency with zero steady-state phase error rather than settling for a small residual offset. That filter, combined with the phase detector gain and VCO gain, sets the loop's two defining numbers: natural frequency ω_n (roughly, how fast the loop responds) and damping ratio ζ (how much it overshoots on the way there).

ζ < 1   underdamped:  fast lock, but overshoot and ringing in phase error
ζ = 1   critically damped: fastest lock with no overshoot
ζ > 1   overdamped:    no overshoot, but sluggish lock

Widening the loop bandwidth (raising ω_n) makes the PLL lock faster and track faster reference changes, but it also lets more of the reference's own phase noise and any noise picked up in the detector through to the output — the classic PLL design trade-off is exactly lock speed and tracking range versus output jitter and noise rejection, and every real PLL design is a negotiation between those two.

Lock range, capture range, and what 'losing lock' means

A PLL that is already locked can continue tracking a reference frequency drift across its lock (tracking) range — often fairly wide, since once locked the feedback correction only has to counter small deviations. Acquiring lock from a cold, unsynchronised start is harder: the capture range, the band of initial frequency offset from which the loop can pull itself into lock at all, is generally narrower than the lock range because the phase detector's usable, monotonic error signal only exists over a limited range before it wraps or saturates. If the reference frequency jumps outside the lock range — or noise is severe enough to push the instantaneous phase error past the detector's linear region — the loop loses lock and has to re-acquire from scratch, which is exactly the momentary glitch you sometimes hear as a click or dropout in FM radio or see as a burst of bit errors in a digital receiver.

Two everyday jobs: carrier recovery and clock recovery

In carrier synchronisation, a receiver for a suppressed-carrier or phase-modulated signal (AM synchronous detection, PSK/QAM demodulation) has no dedicated pilot tone to lock to, so a PLL variant (a Costas loop, for phase-ambiguous carriers) reconstructs a local replica of the transmitter's carrier phase and frequency directly from the modulated signal itself, which is what lets the demodulator multiply the incoming signal down to baseband coherently instead of guessing at an arbitrary phase offset.

In clock and data recovery (CDR), a serial receiver — SATA, USB, Ethernet, any high-speed serial link — has no separate clock wire at all; the timing information is embedded in the data's own transitions. A PLL locks its local clock's phase to those transitions, so it can sample each incoming bit at the centre of its eye, where amplitude and timing noise least affect the decision — losing that lock for even a few bit periods on a fast link corrupts every bit sampled until re-acquisition completes.

Frequently asked questions

What is the difference between a PLL's lock range and its capture range?

Lock range is how far the reference frequency can drift while an already-locked PLL keeps tracking it — typically wide, since only small ongoing corrections are needed. Capture range is the narrower band of initial frequency offset from which an unlocked PLL can pull itself into lock in the first place, limited by the phase detector's usable linear range.

Why does a PLL need an integrator in the loop filter?

Without an integral term, the loop settles for a small residual phase error that produces just enough correction voltage to keep the VCO at the reference frequency. Adding an integrator lets the control voltage keep accumulating until the steady-state phase error is driven to exactly zero, which is what makes the loop a true frequency tracker rather than an approximate one.

How does clock recovery work without a separate clock signal?

The receiver's PLL locks onto the timing information already embedded in the data stream's own signal transitions (edges) rather than a dedicated reference tone. Once locked, the recovered clock tells the receiver exactly when to sample each bit — at the centre of the eye, away from the noisy transition regions — which is essential for any high-speed serial link that doesn't carry a separate clock wire.

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Phase-Locked Loops: How Circuits Lock Onto a Noisy Carrier