Phase-Locked Loop (PLL) Bench (3D)

A phase detector, loop filter and VCO on a real-looking bench: watch the oscilloscope lock, slip cycles and settle with the natural frequency and damping you choose.

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The science

What a phase-locked loop does. A phase detector (PD) compares the phase of an input carrier with the phase of a voltage-controlled oscillator (VCO). The PD output passes through a loop filter and steers the VCO frequency until the VCO follows the input in phase (it is locked).

Model used here (phase domain). Phase error e = θin − θvco. Sinusoidal PD: u = sin(e) (Kd = 1 V/rad near lock). VCO: dθvco/dt = Kvvc relative to the carrier. With loop gain K = KdKv and the active PI filter F(s) = (1 + sτ2)/(sτ1):

e′ = Δω − K(a sin e + x),   x′ = sin(e)/τ1,   a = τ2/τ1.

For small e this is a second-order system: ωn = √(K/τ1), ζ = ωnτ2/2, closed loop H(s) = (2ζωns + ωn2)/(s2 + 2ζωns + ωn2). The error after a phase step is e(t) = Δθ e−ζωnt(cos ωdt − (ζωn/ωd) sin ωdt), ωd = ωn√(1−ζ2). The 3 dB bandwidth is ωn√(1 + 2ζ2 + √((1 + 2ζ2)2 + 1)); the noise bandwidth is BL = (ωn/2)(ζ + 1/(4ζ)).

Lock ranges. First-order loop (no filter): e′ = Δω − K sin e has a stable solution exactly when |Δω| < K (the hold-in range), then sin e = Δω/K. The PI loop has no static error, so its hold-in range is set by the VCO tuning range. The lock-in range (a frequency step handled without a cycle slip) is often quoted as 2ζωn; the graph compares that rule of thumb with the largest step this simulation can take before |e| reaches π. The two are defined differently, so they differ by a factor that depends on ζ: the rule of thumb is conservative.

Simplifications (honest list). No ripple at 2ω0 from the multiplier PD (a phase-domain model has none); no digital or charge-pump PD; the loop filter is an ideal PI with anti-windup at the VCO limits; the VCO is linear; the input amplitude is constant; noise is white phase noise at the PD input applied as a zero-order hold each 50 µs. The 500 Hz carrier on the scope is a display choice; loop dynamics do not depend on it. Time runs in slow motion so you can watch it.

Independent numerical checks run in the page. (1) Simulated phase step vs the closed form. (2) Closed-loop |H(jω)| measured by driving the nonlinear simulation with a small phase sine and demodulating the VCO phase, vs the formula. (3) First-order loop: 970 rad/s locks with sin e = 0.97 and 1030 rad/s slips for K = 1000 rad/s. (4) Monte-Carlo VCO phase variance for white input noise vs S·BL.

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Phase-step error against the closed form
Closed-loop response |H| (Bode magnitude)
Phase portrait of frequency steps
Lock-in estimate against damping

🔁 Phase-Locked Loop (PLL)

A PLL is a feedback control system that makes one oscillator lock its phase and frequency to another. From FM radio demodulators to CPU clock generators, PLLs are one of the most widely used circuits in electronics.

What It Demonstrates

A 2nd-order PLL has three blocks: (1) a Phase Detector that produces a voltage proportional to the phase difference between input and VCO, (2) a Loop Filter that shapes the feedback — a PI (proportional-integral) filter gives zero steady-state phase error, (3) a VCO whose frequency shifts proportionally to its input voltage. The loop dynamics are governed by two parameters: natural frequency ωn (how fast it locks) and damping ratio ζ (how oscillatory the transient is). For ζ = 0.707 (a common design choice) the loop settles quickly without ringing. For ζ < 0.5 the phase error overshoots and rings before settling.

Did You Know?

Every modern processor uses a PLL to multiply a low-frequency reference clock (e.g. 100 MHz crystal) up to GHz speeds (3–5 GHz). GPS receivers use a PLL to lock onto each satellite carrier (1575.42 MHz for L1). The invention of the PLL is credited to Henri de Bellescize, who described it in a 1932 French paper on homodyne reception.

About this simulation

Written by MySimulator Team · Reviewed by MySimulator Editorial Review

Last updated: 5 July 2026

Frequently asked questions

What do damping ratio ζ and natural frequency ωn actually control?

Together ζ and ωn set the loop's second-order response, the same way they would for a mechanical spring-mass-damper system. Natural frequency ωn sets how fast the loop reacts — a higher ωn locks faster but tracks more of the input noise. Damping ratio ζ sets how oscillatory the transient is: ζ = 0.707 gives a quick, near-optimal response with minimal overshoot, ζ well below 0.5 produces visible ringing in the phase-error plot before it settles, and ζ above 1 gives a sluggish, overdamped approach to lock.

Where are phase-locked loops used in real electronics?

PLLs are one of the most common building blocks in electronics. Clock generation and frequency synthesis circuits use a PLL to multiply a stable low-frequency crystal reference up to the multi-gigahertz clock speeds modern processors need. Digital receivers use PLL-based clock and data recovery (CDR) circuits to re-derive a clean bit clock from a noisy incoming data stream. FM radio demodulators use a PLL to track the carrier's instantaneous phase and recover the audio signal, and GPS receivers use PLLs to lock onto each satellite's carrier frequency for precise ranging.

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