NCFET Energy Landscape & Hysteresis Loop — a 2D Phase Portrait

Ordinary transistors can never switch faster than 60 millivolts per decade of current at room temperature — the Boltzmann tyranny that limits how far supply voltage, and therefore power, can be scaled down. Stacking a ferroelectric layer such as doped HfO₂ in series with the gate oxide creates a region of genuine negative capacitance in the ferroelectric's Landau free-energy landscape, which internally amplifies the gate voltage's effect on the channel surface potential. Rather than rendering the gate stack in 3D, this view solves the same coupled ferroelectric/MOS charge-continuity equations and plots them the way device physicists actually read them: as a tilting double-well energy landscape and a live Q-V_g hysteresis loop, alongside a flat 2D tile array standing in for the microscopic dipole domains — with a one-click toggle back to a baseline MOSFET for direct comparison.