This is a 2D phase-portrait view of the same negative-capacitance FET (NCFET) model: a thin ferroelectric layer (HfO₂-style) in series with the gate oxide. Its free energy follows the Landau-Devonshire form U(P) = a·P² + b·P⁴, and in the ferroelectric phase a < 0, giving a double-well energy landscape and a region of negative slope dV/dQ — a genuine negative capacitance.
V_FE(Q) = t_FE·(a·Q + b·Q³) (Landau equation of state)
V_MOS(Q) = Q / C_ox (linear channel capacitor)
V_g = V_FE(Q) + V_MOS(Q) (series charge continuity)
F(Q) = t_FE·(a·Q²/2 + b·Q⁴/4) + Q²/(2·C_ox) − V_g·Q (potential; dF/dQ = 0 solves the line above)
Instead of rendering the ferroelectric slab in 3D, this view plots that potential F(Q) directly — a tilting double well whose minimum tracks the charge as V_g sweeps — solved by the same warm-started Newton iteration (which is why sweeping up/down traces slightly different paths, a real hysteretic NCFET artifact). The right-hand panel plots the resulting Q vs. V_g curve live as you sweep, tracing out the actual hysteresis loop area — the standard textbook diagnostic for whether a gate stack is capacitance-matched. The strip along the top renders the same 8×8 dipole-domain array as flat 2D tiles instead of 3D cones, using an identical per-domain coercive-bias model.
A = dψ_s/dV_g = 1 / (1 + C_ox·t_FE·(a + 3b·Q²))
Because a < 0, the denominator drops below 1 and A > 1: the ferroelectric layer amplifies the gate's pull on the channel surface potential ψ_s. Since subthreshold current follows I_ds ∝ exp(ψ_s/V_T), the swing becomes SS = (60 mV/dec) / A — below the fundamental Boltzmann limit that traps ordinary CMOS at 60 mV/decade at room temperature.
- Vg — sweeps the gate bias; the well tilts and the domain tiles switch as local charge crosses each tile's coercive threshold.
- NC strength — magnitude of the Landau a-coefficient; stronger negative capacitance gives a deeper double well, bigger internal gain and a wider hysteresis loop.
- tFE — ferroelectric layer thickness; thicker layers couple more strongly to the MOS capacitor.
- Mode toggle — switches the ferroelectric layer out of the circuit, collapsing the well to a single parabola pinned to the 60 mV/decade limit (A = 1).