RC Ladder Interconnect Delay (2D)

Every real wire — an on-chip interconnect, a length of coax, a network cable — carries a signal that does not arrive everywhere at once. This 2D simulator models a chain of N resistor-capacitor stages as a real coupled ODE, numerically integrated node by node, laid out as a pannable schematic with a live four-trace oscilloscope and an instantaneous per-node voltage profile. Live readouts compare the simulated 50%-arrival delay at the far end against the analytical Elmore delay formula that circuit designers use to estimate interconnect timing without solving the full system by hand.