JTAG TAP State Diagram & Linear Scan Register (2D)

Almost every embedded chip exposes a four-wire IEEE 1149.1 debug port whose 16-state Test Access Port machine shifts bits through a boundary-scan register wrapped around every pin. This 2D companion draws the exact same finite-state automaton directly as a state-transition graph — the classic two-loop TAP diagram with every δ(state, TMS) edge labeled — instead of orbiting a 3D chip die, and lays the boundary-scan register out as a straight left-to-right strip of 4–16 cells instead of a ring. Drive real TMS pulses to walk the state graph by hand, shift a live bit pattern down the register, and switch into EXTEST mode to watch the pin strip get forced to arbitrary values — the same debug-port attack that bypasses secure boot, seen from a genuinely different 2D angle: a graph and a linear register, not a projected 3D scene.