5-Stage CPU Pipeline: Hazards & Forwarding

This simulator renders the classic 5-stage RISC instruction pipeline (Fetch, Decode, Execute, Memory, Write-Back) as a live 3D animation. A randomly generated instruction stream — a mix of ALU operations, loads and stores, seeded with deliberate register dependencies — flows through the datapath one cycle at a time. Toggle data forwarding to see the pipeline's hazard-detection logic in action: with forwarding off, any true register dependency stalls the pipeline until the producing instruction reaches write-back; with forwarding on, most stalls vanish except the one-cycle bubble a load-use hazard always costs, because a load's value genuinely doesn't exist until the memory stage completes. Live readouts track cycle count, retired instructions, injected stall bubbles, forwarding events and the resulting instructions-per-cycle.