5-Stage CPU Pipeline: Hazards & Forwarding (2D)

This simulator renders the classic 5-stage RISC instruction pipeline (Fetch, Decode, Execute, Memory, Write-Back) as a live 2D pipeline diagram: rows are instructions in program order, columns are clock cycles, and each cell shows which stage that instruction occupied that cycle. A randomly generated instruction stream — a mix of ALU operations, loads and stores, seeded with deliberate register dependencies — is decoded, hazard-checked and retired one cycle at a time, exactly as a real in-order core would. Toggle data forwarding to see the pipeline's hazard-detection logic in action: with forwarding off, any true register dependency stalls the pipeline (repeated ID cells, then a grey bubble cell) until the producing instruction reaches write-back; with forwarding on, an animated blue arrow bypasses the EX/MEM result straight into the dependent instruction's EX stage and most stalls vanish, except the one-cycle bubble a load-use hazard always costs. Live readouts track cycle count, retired instructions, injected stall bubbles, forwarding events, and separately-accumulated CPI for forwarding on vs. off so the performance difference is directly measurable.