JTAG TAP State Diagram & Linear Scan Register (2D): Understanding Boundary-Scan Testing

What is JTAG Boundary-Scan Testing?

JTAG (Joint Test Action Group) is an industry-standard interface used to test and debug integrated circuits. The TAP (Test Access Port) controller, a key component of JTAG, manages the communication between test equipment and devices under test.

Boundary-scan testing uses this interface to test interconnections on printed circuit boards by shifting data through scan chains that are embedded in the device.

The TAP State Diagram

The TAP state diagram illustrates the sequence of states a JTAG controller goes through during various operations, such as testing and configuration.

Each state is represented by a node in the diagram, with transitions between nodes indicating the flow of control.

Linear Scan Register

The linear scan register (LDR) is a shift register that holds test data for boundary-scan testing. It can be shifted either left-to-right or right-to-left to capture and drive test patterns.

By manipulating the TAP controller, you can control which cells in the LDR are accessed during each operation.

Controlling JTAG Operations

Users can interact with the state diagram by pulsing the TMS (Test Mode Select) signal to step through different states.

The linear scan register allows users to shift individual bits or the entire register, and switch between SAMPLE/PRELOAD and EXTEST modes for reading or driving pins.

Frequently asked questions

Try it live

Everything above runs in your browser — open JTAG TAP State Diagram & Linear Scan Register (2D) and change the parameters while it is running. Nothing is installed, nothing is uploaded, the whole model lives in one tab.