Flip-Flop: One Bit of Digital Memory

Memory from two gates that disagree with each other

Every logic gate you meet in an introductory course is combinational: its output depends only on its current inputs, nothing more. Wire the output of one NOR gate into the input of a second NOR gate, and the second gate's output back into the first, and something new happens — the pair develops two stable states that persist even after the inputs that put it there are removed. That circuit is the SR (set-reset) latch, and it is the smallest unit of digital memory: one bit, held not in a capacitor's charge but in the mutual disagreement of two gates.

S=1, R=0  → Q sets to 1, stays 1 after S returns to 0
S=0, R=1  → Q resets to 0, stays 0 after R returns to 0
S=0, R=0  → Q holds whatever it was — this is the memory
S=1, R=1  → both outputs forced equal — the forbidden state

Why S=1, R=1 is forbidden

The latch's two outputs, Q and its complement not-Q, are supposed to always disagree. Forcing both S and R active drives both gates toward the same output value, breaking that complementary relationship. Worse, when both inputs release at the same instant, which gate settles first is decided by microscopic timing differences between the two gates — a genuine race condition with an unpredictable winner. Real designs simply never allow S and R to be asserted together.

From level-sensitive latch to edge-triggered flip-flop

A plain SR or D latch is transparent: while its enable line is high, its output follows its input immediately, which is dangerous in a large circuit — a change can race through several latches in one clock phase before you want it to. The fix is a flip-flop: an edge-triggered circuit, typically built from a master latch and a slave latch in series, driven by complementary clock phases, so the whole two-stage structure only accepts a new value at the single instant the clock transitions from low to high (or high to low, depending on design).

The most common variant is the D flip-flop: whatever voltage is on its D input at the clock edge becomes the new Q, and Q holds that value rock-solid until the next edge, completely insulated from any noise or changes on D in between. This single behaviour — sample once per clock, hold until told otherwise — is what lets digital designers reason about circuits one clock cycle at a time instead of worrying about a continuous, analogue-like cascade of changes.

JK and T flip-flops

The JK flip-flop extends the SR idea but resolves the forbidden case usefully: J=K=1 at a clock edge makes the output toggle instead of entering an undefined state. Tie J and K together permanently high and you get the T (toggle) flip-flop, which flips its output on every clock edge — the building block of binary ripple counters, where each stage's output clocks the next stage and divides the frequency by two again.

From one bit to a whole processor

A modern CPU register is simply many D flip-flops sharing one clock line, each holding one bit of a word; a register file is a bank of such registers with multiplexers selecting which one is read or written. Pipeline stages in a processor are separated by rows of flip-flops that latch the intermediate results once per clock, which is exactly what allows different instructions to be at different stages of execution simultaneously without their signals corrupting each other. Every clocked digital system, from a simple counter to a multi-billion-transistor chip, is built from this one repeated idea: combinational logic computing a next state, and flip-flops remembering it until the next tick.

Frequently asked questions

Try it live

Everything above runs in your browser — open Flip-Flop and change the parameters while it is running. Nothing is installed, nothing is uploaded, the whole model lives in one tab.