Register Allocation: Graph Coloring Visualizer

Every compiler back end faces the same problem: source code implies an unlimited number of temporary values, but the target CPU has only a handful of physical registers. This simulator runs the classic Chaitin-style solution end to end and shows every step in 3D. First a real backward liveness analysis walks a small three-address-code program to find which virtual registers are simultaneously alive; any two that are alive at the same time become an edge in an interference graph. The allocator then simplifies that graph — repeatedly removing low-degree nodes onto a stack, or optimistically removing a high-degree one when stuck — and finally pops the stack to assign each register the lowest free color among its already-colored neighbours, marking a node red when no physical register is left and it has to spill to memory. Change the program, the number of physical registers, and the playback speed to see exactly when and why a compiler is forced to spill.