8-Bit Ripple-Carry Adder | mysimulator.uk

A half adder, then a full adder

Binary addition of two single bits needs two outputs: the sum bit and a carry bit, since 1+1 overflows a single bit. A half adder computes both with two gates — an XOR for the sum, an AND for the carry:

Sum   = A XOR B
Carry = A AND B

That handles the least significant bit, but every higher bit position must also absorb a carry in from the position below it — three inputs, not two. A full adder extends the half adder to accept a carry-in Cin alongside A and B, and produces a sum bit and a carry-out:

Sum  = A XOR B XOR Cin
Cout = (A AND B) OR (Cin AND (A XOR B))

The second equation says: a carry is generated either when both A and B are 1 outright, or when exactly one of A, B is 1 and there was already a carry coming in to push the sum over 1. A full adder is built from two half adders plus an OR gate, or directly from five to nine logic gates depending on the gate library.

live demo · 8 full adders chained by their carry signals● LIVE

Ripple-carry: chaining 8 of them

An 8-bit adder chains eight full adders, wiring the carry-out of bit position i directly into the carry-in of bit position i+1. This is the ripple-carry adder — named because a carry generated at the low-order bit must physically propagate, or ripple, through every higher stage before the final result is valid, exactly like this simulation's bit-toggle animation shows.

bit:     7    6    5    4    3    2    1    0
       ┌────┬────┬────┬────┬────┬────┬────┬────┐
Cin →  │ FA │←Cout│ FA │←Cout│ FA │←Cout│ FA │←Cout ... →Cout(final)
       └────┴────┴────┴────┴────┴────┴────┴────┘
              each FA: Sum = A⊕B⊕Cin, Cout = AB + Cin(A⊕B)

The simplicity is also the design's weakness. Each full adder cannot produce a correct sum bit until its carry-in has settled, so the worst-case propagation delay of an n-bit ripple-carry adder grows linearly with n — roughly 2n gate delays, since a carry has to pass through the AND-OR carry logic of every stage in sequence. For 8 bits that is a modest 16 gate delays and entirely fine for a slow or moderate clock; for a 64-bit ALU it becomes the critical path that limits the whole processor's clock speed.

Why real CPUs don't use ripple-carry at 64 bits

The fix is to stop waiting for the carry to ripple and instead compute it directly. A carry-lookahead adder defines, for each bit, a generate signal G = A·B (this position produces a carry regardless of Cin) and a propagate signal P = A⊕B (this position passes an incoming carry through). Every carry bit can then be written as a sum-of-products of G's and P's from lower positions — no longer a chain, but a shallow tree of gates, which collapses the O(n) delay to roughly O(log n) at the cost of considerably more wiring and gates. Real ALUs typically use a hybrid: lookahead within 4-bit blocks, ripple (or a second level of lookahead) between blocks, trading gate count against delay.

Reading the result three ways

Once the 8 sum bits and the final carry-out have settled, the raw bit pattern is just a sequence of 0s and 1s with no inherent meaning — it is the interpretation that assigns it a value. Read as unsigned binary, bit i contributes 2^i, giving a range of 0 to 255 for 8 bits; a carry-out of 1 signals the true sum exceeded 255 and overflowed the register. Read as two’s complement signed binary, the top bit is a sign bit worth −2⁷ instead of +2⁷, giving a range of −128 to 127, and overflow is instead detected by comparing the carry into the top bit against the carry out of it. The same adder circuit computes both interpretations simultaneously — addition in two's complement is bit-for-bit identical to unsigned addition, which is precisely why two's complement became the universal choice for signed integers.

Frequently asked questions

Why does the carry take time to propagate through all 8 bits?

Because each full adder's carry-out depends on its own carry-in, and that carry-in is the carry-out of the stage below it. In a ripple-carry design nothing about that dependency chain can be skipped, so the correct final sum is only guaranteed after a carry signal has had time to pass through every one of the 8 stages — the design's defining trade-off between simplicity and speed.

Why do real CPUs use faster adders than ripple-carry?

At 8 bits, roughly 16 gate delays is negligible. At 32 or 64 bits, that delay would dominate the CPU's clock period. Carry-lookahead adders precompute carries from generate/propagate signals in a shallow gate tree instead of a linear chain, trading extra gates for a delay that grows logarithmically instead of linearly with the bit width.

How does the same circuit give both a signed and unsigned result?

The full-adder logic never looks at sign — it just adds bit patterns. Two's complement is designed so ordinary binary addition of two negative-or-positive numbers produces the mathematically correct signed result automatically; only the overflow-detection rule differs between the unsigned reading (watch the final carry-out) and the signed reading (compare the carry into and out of the top bit).

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The 8-Bit Ripple-Carry Adder: Full Adders, Carry Chains and Why CPUs Moved On