Register Allocation via Graph Coloring (2D)

Compilers cannot give every variable its own physical register — CPUs only have a handful (K), while a function may juggle dozens of live values. The classic solution, due to Chaitin, models the problem as graph coloring: build an interference graph where virtual registers that are live at the same time are connected, then try to K-color it so connected registers get different physical registers. This 2D simulator runs the real simplify/select algorithm — repeatedly stripping low-degree, guaranteed-colorable nodes onto a stack, optimistically spilling when none remain, then popping the stack and assigning the lowest free color — over a live planar spring-electrical graph embedding computed entirely in two dimensions, so denser or larger graphs visibly tangle and cross the way a true planar layout must, distinct from a free-floating 3D embedding of the same graph. Adjust K, graph size and density to see how allocation pressure changes both the colouring outcome and how crowded the flattened layout becomes.