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🧩 MESI Cache Coherence Protocol Explorer

See how the MESI protocol keeps multiple CPU cores' caches consistent as they read and write a shared memory address, tracking cache lines through Modified, Exclusive, Shared, and Invalid states.

Computer Science3DModerate60 FPS

The simulation shows several CPU cores sharing one memory address, with each core's cache line visibly transitioning between Modified, Exclusive, Shared, and Invalid states as bus read and write transactions are snooped.

🔬 What It Demonstrates

🎮 How to Use

Trigger a read or write from any core using the per-core controls and watch the resulting bus transaction propagate, invalidating or updating other cores' cache line states accordingly.

💡 Did You Know?

A cache line ping-ponging between two cores' Modified states on every write, known as false sharing when the variables are unrelated, can slow a multithreaded program down by 10x or more without producing a single incorrect result.

⚙ Under the hood

See how the MESI protocol keeps multiple CPU cores' caches consistent as they read and write a shared memory address, tracking cache lines through Modified, Exclusive, Shared, and Invalid states.

computer-architecturecache-coherencemesi-protocolmulticorememory-systemsparallel-computingmicroarchitecture

3D · Three.js / WebGL renderer · 60 FPS target · runs fully client-side, no install