Why Simulate Electronics?
Electronic circuits are among the most abstract engineering artifacts humans have built. A modern CPU contains billions of transistors. A WiFi frame encodes information across 52 orthogonal sub-carriers simultaneously. RF phase-locked loops synchronise to signals arriving at fractions of a radian. These are not things you can visualise by reading a datasheet.
Simulation bridges that abstraction gap. Watching a ripple-carry propagate through eight full-adder stages — seeing the carry bit light up cell by cell — installs an intuition that "carry propagation delay limits clock speed" that no textbook sentence can replicate. The same logic applies across the whole electronics stack, from Boolean gates to spectral OFDM sub-carriers.
Layer 1: Boolean Logic
Logic Gates — The Atoms of Computation
All digital logic reduces to seven primitive gates: AND, OR, NOT, NAND, NOR, XOR, and XNOR. The Logic Gates simulation renders each gate in IEEE standard symbols, animates signal pulses travelling through them, and shows a live truth table. You can chain gates manually to build combinational circuits and watch the output propagate.
Logic Gates
All 8 gate types (AND/OR/NOT/XOR/NAND/NOR/XNOR/BUF) in IEEE symbols. Animated signal pulses, live truth table, configurable input toggles. See how every Boolean function decomposes to NAND.
8-Bit Ripple-Carry Adder
Full adder chain for two 8-bit integers. Watch the carry bit propagate stage by stage. Overflow flag highlights. Output shown in binary, hexadecimal, and decimal simultaneously.
Boolean Algebra Identities
De Morgan: ¬(A ∧ B) = ¬A ∨ ¬B (NAND completeness)
De Morgan: ¬(A ∨ B) = ¬A ∧ ¬B (NOR completeness)
Full adder: Sum = A ⊕ B ⊕ Cᵢₙ
Full adder: Cₒᵤₜ = (A ∧ B) ∨ (Cᵢₙ ∧ (A ⊕ B))
Ripple carry delay: tₚ ≈ n · t_FA (n = number of stages)
A key insight the 8-bit adder makes tactile: carry propagation is the fundamental bottleneck in binary arithmetic. The signal must "ripple" through all eight full-adder stages before the result is valid. This is why real CPUs use carry-lookahead adders (CLA) or carry-select adders — they compute carry bits in parallel rather than sequentially. Understanding the ripple-carry first makes the optimisation compelling.
Layer 2: Semiconductor Devices
Transistor — The Switch That Built the World
The transistor is arguably the most important invention of the 20th century. A BJT (bipolar junction transistor) uses a small base current to control a large collector–emitter current; a MOSFET uses a gate voltage to control drain–source current without drawing base current at all. Both enable amplification and switching — the two primitive operations from which all analog and digital electronics descend.
Transistor BJT / MOSFET
NPN BJT characteristic I–V family with load-line and Q-point animation. N-channel MOSFET output curves. Active / saturation / cutoff regions colour-coded. Slide Vcc, Rc, and Ib to watch the Q-point move.
RC Filters — Bode Diagrams
Low-pass, high-pass, and band-pass RC filters on a log-frequency Bode diagram. −3 dB corner marker, phase shift, animated time-domain signals showing input vs output. Tune R and C in real time.
BJT & RC Filter Key Equations
BJT: Ic = β · Ib (active region)
MOSFET saturation: Id = (μₙCₒₓ/2)·(W/L)·(Vgs − Vth)²
RC low-pass: H(jω) = 1 / (1 + jωRC)
Corner frequency: fc = 1 / (2πRC)
At dc: |H| = 1. At fc: |H| = 1/√2 ≈ −3 dB
Phase shift at fc: φ = −45°
The Bode diagram is one of the most powerful tools in electrical engineering — it shows how a circuit responds at every frequency simultaneously on a logarithmic axis. The RC filter simulation lets you tune the corner frequency by adjusting R and C, and watch the diagram update in real time. The same RC network appears in EEG amplifiers, audio crossovers, debouncing circuits, and power supply decoupling — making this one of the most universally applicable simulations in the collection.
Layer 3: Analog–Digital Interface
ADC/DAC — Bridging Two Worlds
Every microphone, camera, radio, and sensor converts a continuous analog signal into discrete digital samples — and back again. This sampling–quantisation boundary is where information theory (Nyquist's theorem) meets hardware reality (quantisation noise). The ADC/DAC simulation makes the aliasing artefact visible: sample a 900 Hz sine wave at 1000 samples/second and the output appears as a 100 Hz signal — exactly the alias predicted by Nyquist.
ADC / DAC Sampling
Continuous wave, sample points, and staircase reconstruction visualised together. Aliasing detection, adjustable sampling rate, quantisation from 1–12 bits. Nyquist theorem and quantisation noise equation live.
Digital Filter Designer
FIR and IIR filter design (Butterworth, Chebyshev, windowed-sinc). Bode diagrams, pole-zero plot in the Z-plane, real-time signal filtering. See how filter order trades stopband attenuation against group delay.
Sampling & Nyquist Theorem
Nyquist: fs ≥ 2 · fₘₐₓ (no aliasing condition)
Alias frequency: fₐ = |fs·round(f/fs) − f|
Quantisation noise: σ² = Δ²/12 (uniform, Δ = step size)
SQNR ≈ 6.02·N + 1.76 dB (N = bits per sample)
CD audio: fs = 44.1 kHz, N = 16 bits → SQNR ≈ 98 dB
Quantisation noise is the fundamental price of digitisation: every analog value gets rounded to the nearest representable level. With N bits, you have 2ᴺ levels. Each additional bit doubles the number of levels and improves the signal-to-quantisation-noise ratio by roughly 6 dB. This is why professional audio uses 24-bit recording (144 dB theoretical SQNR) while consumer earbuds run 16-bit codec output (96 dB). The ADC/DAC simulator makes this trade-off tangible.
Layer 4: Digital Communications
OFDM — How WiFi and 4G Encode Data
Orthogonal Frequency Division Multiplexing is the modulation scheme used in WiFi, LTE, 5G-NR, and digital television. Instead of putting all the data on one carrier, OFDM splits the channel into dozens or hundreds of narrow sub-carriers, each carrying a small fraction of the data stream. The sub-carriers are spaced at exactly 1/T Hz apart, making them mathematically orthogonal so they don't interfere with each other — which is why an IFFT (inverse FFT) can generate them simultaneously.
OFDM & WiFi Sub-carriers
52 orthogonal sub-carriers generated by IFFT. Configurable multipath echoes, cyclic prefix (eliminates ISI), time-domain and frequency-domain views, constellation diagram. IEEE 802.11 sub-carrier spacing model.
Phase-Locked Loop (PLL)
VCO, loop filter, and phase detector in real-time. Phase error convergence curve, lock-acquisition animation, jitter spectrum. Sliders for Kv, ωₙ, ζ (damping ratio). Used in every radio transmitter/receiver.
OFDM Sub-carriers & Phase-Locked Loop
OFDM: xₙ = (1/N) Σ Xₖ · exp(j2πkn/N) (IDFT synthesis)
Orthogonality: ∫₀ᵀ cos(2πnf₀t)·cos(2πmf₀t) dt = 0 (n≠m)
Sub-carrier spacing: Δf = 1/T (T = OFDM symbol duration)
PLL open-loop gain: G(s) = Kv · F(s) / s
Natural frequency: ωₙ = √(Kv·Kₚ/τ₂)
Lock range: |Δω| ≤ Kv (VCO gain determines pull-in range)
The cyclic prefix in OFDM is an elegant engineering solution to a theoretical problem: a real channel produces multipath echoes that blur symbols together (intersymbol interference). By copying the last T_g seconds of each symbol to its front, OFDM turns linear convolution into circular convolution — transforming the difficult inter-symbol problem into a simple per-sub-carrier multiplication in the frequency domain. The OFDM simulation lets you toggle the cyclic prefix on and off and watch the constellation scatter as multipath destroys orthogonality without it.
Complete Electronics Collection
All electronics and signal processing simulations work fully offline via the PWA cache. Try them on a phone or tablet — the Bode diagrams and constellation plots are optimised for touch.
Logic Gates
AND / OR / NOT / XOR / NAND / NOR / XNOR / BUF with live truth table
8-Bit Adder
Ripple-carry full-adder chain — carry propagation visible stage by stage
Transistor BJT/MOSFET
NPN BJT and N-MOSFET I–V characteristic curves with interactive Q-point
RC Filters
LP / HP / BP Bode diagrams with real-time tuning and time-domain waveforms
ADC / DAC
Nyquist sampling, aliasing detection, 1–12 bit quantisation noise
Digital Filter
FIR / IIR (Butterworth, Chebyshev, windowed-sinc) Bode + Z-plane plot
OFDM & WiFi
52 orthogonal sub-carriers, multipath, cyclic prefix, constellation
Phase-Locked Loop
VCO lock-acquisition, phase error convergence, jitter spectrum
Algorithms & Methods
Next in the series: Learning #17 — Quantum Mechanics & Wave Functions dives into the mathematics of quantum phenomena — Schrödinger's equation, quantum tunnelling, the double-slit experiment, and the quantum circuit model — linking each concept to an interactive simulation.