Click bits to toggle 0/1 · Watch carry propagate · See binary, hex, decimal results
An interactive visualisation of an 8-bit ripple-carry adder — the fundamental building block of every CPU's arithmetic logic unit. Toggle bits, watch carries propagate, and see binary, hexadecimal and decimal results update live.
How a full adder computes sum and carry-out from two input bits and a carry-in, then chains eight stages together so each carry ripples to the next. The critical path through the carry chain determines the adder's maximum clock speed.
Click individual bits of A and B to toggle them on or off. Watch the carry chain flash through all 8 stages. Read the final result in binary, hex and decimal below the circuit.
The ripple-carry adder is the simplest binary adder design, but its O(n) carry propagation limits speed. Modern CPUs use carry-lookahead or Kogge–Stone adders that compute all carries in O(log n) time.
This simulation models an 8-bit ripple-carry adder, the arithmetic core of a CPU's ALU. It chains eight identical full-adder stages, one per bit position. Each stage computes a sum bit and a carry-out from two input bits and an incoming carry, using the Boolean equations S = A ⊕ B ⊕ Cₜₙ and Cₒₕₜ = (A·B) + (B·Cₜₙ) + (A·Cₜₙ). The carry ripples from bit 0 to bit 7.
Click the bit buttons in the Input A and Input B panels to toggle each bit between 0 and 1; the decimal value of each operand updates live. The Sum panel reports the result as a 9-bit binary string, decimal, hexadecimal, and an overflow flag (the carry out of bit 7). Reset and Random buttons set the operands. Adders like this underpin every addition, subtraction, and address calculation a processor performs.
What is a ripple-carry adder?
A ripple-carry adder is a digital circuit that adds two binary numbers by connecting a chain of full adders, one for each bit. The carry produced by each stage feeds into the next, so the carry signal "ripples" along the chain from the least significant bit to the most significant. This simulation uses eight such stages to add two 8-bit numbers.
What is the difference between a half adder and a full adder?
A half adder adds just two input bits and produces a sum and a carry, but it cannot accept an incoming carry. A full adder adds three bits, the two operands plus a carry-in, which is what lets stages be chained together. This adder is built entirely from full adders so carries can propagate.
How does a single full-adder stage work?
Each stage computes the sum bit as S = A ⊕ B ⊕ Cₜₙ, the exclusive-OR of the two input bits and the carry-in. The carry-out is Cₒₕₜ = (A·B) + (B·Cₜₙ) + (A·Cₜₙ), which is 1 whenever at least two of the three inputs are 1. That carry-out becomes the carry-in for the next bit.
The Input A and Input B panels each show eight bit buttons running from bit 7 down to bit 0; clicking one toggles it between 0 and 1. The Sum panel displays the result in binary, decimal and hex, plus an overflow indicator. The Reset button clears both numbers to zero, and the Random button fills both with random bits.
Adding two 8-bit numbers can produce a value larger than 255, the maximum an 8-bit register holds. The extra ninth bit captures the final carry out of bit 7. Since each operand can reach 255, the largest possible sum is 510, which needs nine bits to represent fully.
The overflow flag shows the carry out of the most significant bit, labelled C₈. When the unsigned sum exceeds 255 it sets to "Yes (C₈=1)", meaning the answer no longer fits in 8 bits. In a real CPU this carry bit is stored in the status register and used for multi-byte arithmetic and comparisons.
Yes, the logic is faithful: it implements true full-adder Boolean equations and a left-to-right carry chain exactly as a hardware ripple-carry adder would. The main simplification is timing; the animation flashes the carry path for clarity rather than reproducing real gate propagation delays measured in nanoseconds.
Because each stage must wait for the carry from the stage below it, the worst-case delay grows linearly with the number of bits, giving O(n) propagation time. For wide words this critical path through the carry chain limits how fast the circuit can be clocked.
Carry-lookahead adders compute carries in parallel from generate and propagate signals, reaching all carries in roughly O(log n) time. Other fast designs include carry-select, carry-save, and parallel-prefix adders such as Kogge-Stone, all of which trade extra logic for shorter delay. Modern processors rely on these instead of plain ripple-carry.
Computers subtract by adding the two's complement of the second operand: invert its bits and add 1. The same adder hardware handles subtraction once the input is negated, which is why a single ripple-carry adder, combined with inverters and a carry-in, can perform both addition and subtraction in an ALU.