VCO · Phase detector · Loop filter · Lock range · Jitter
A PLL is a feedback control system that makes one oscillator lock its phase and frequency to another. From FM radio demodulators to CPU clock generators, PLLs are one of the most widely used circuits in electronics.
A 2nd-order PLL has three blocks: (1) a Phase Detector that produces a voltage proportional to the phase difference between input and VCO, (2) a Loop Filter that shapes the feedback — a PI (proportional-integral) filter gives zero steady-state phase error, (3) a VCO whose frequency shifts proportionally to its input voltage. The loop dynamics are governed by two parameters: natural frequency ωn (how fast it locks) and damping ratio ζ (how oscillatory the transient is). For ζ = 0.707 (critically damped) the loop settles quickly without ringing. For ζ < 0.5 the phase error overshoots and rings before settling.
Start with the default settings and watch the phase error converge to zero — the PLL acquires lock. Increase the input noise slider and observe how jitter increases. Set ζ to 0.2 (underdamped) and watch the oscillatory acquisition with ringing. Try a large initial phase offset (π) and a small loop bandwidth — the acquisition takes longer. Switch from 1st-order to PI filter to see how the PI eliminates steady-state frequency offset (integral action). The Bode plot updates live to reflect the filter shape.
Every modern processor uses a PLL to multiply a low-frequency reference clock (e.g. 100 MHz crystal) up to GHz speeds (3–5 GHz). GPS receivers use a PLL to lock onto each satellite carrier (1575.42 MHz for L1). The invention of the PLL is credited to Henri de Bellescize, who described it in a 1932 French paper on homodyne reception. The PLL in the original Apollo guidance computer locked to 2048 Hz pulses from an inertial gyroscope.
This simulation models a 2nd-order phase-locked loop: a phase detector compares the phase of a noisy input carrier against a voltage-controlled oscillator (VCO), a loop filter shapes that error into a control voltage, and the VCO shifts its own phase to track the input. The loop's response is set by two parameters, natural frequency ωn and damping ratio ζ, and you can switch the loop filter between a first-order, PI, and lag-lead design to see how each shapes acquisition and steady-state error.
Three live views of the same loop: a phase-error time series (green once locked, orange while acquiring), a phasor diagram showing the input and VCO phase vectors converging, and a Bode magnitude plot of the currently selected loop filter. The stats panel reports live phase error, jitter (RMS), pull-in range, and estimated acquisition time.
Pick a loop filter (1st Order, PI, or Lag-Lead), then drag VCO Gain K₀, Phase Detector Gain Kd, Damping Ratio ζ and Loop Bandwidth ωn to reshape the dynamics. Increase Input Noise to add carrier jitter, or push the Initial Phase Offset toward π to force a harder acquisition. Try ζ = 0.707 for a quick, non-oscillatory lock versus ζ = 0.2 for an underdamped, ringing acquisition.
Every modern CPU uses a PLL to multiply a slow crystal reference (often 100 MHz) up to multi-gigahertz clock speeds, and FM radios use a PLL demodulator to recover audio directly from the carrier's phase changes. The PLL itself dates to 1932, when French engineer Henri de Bellescize first described synchronous (homodyne) reception.
The simulation models a classic 2nd-order PLL: a phase detector that outputs Kd·sin(phase error) between the input and VCO phase, a loop filter (selectable as first-order, PI, or lag-lead) that filters that error signal into a control voltage, and a VCO whose output phase advances by an amount proportional to VCO gain K₀ times the filtered control voltage. The VCO's phase feeds back into the phase detector, closing the loop.
Together ζ and ωn set the loop's second-order response, the same way they would for a mechanical spring-mass-damper system. Natural frequency ωn sets how fast the loop reacts — a higher ωn locks faster but tracks more of the input noise. Damping ratio ζ sets how oscillatory the transient is: ζ = 0.707 gives a quick, near-optimal response with minimal overshoot, ζ well below 0.5 produces visible ringing in the phase-error plot before it settles, and ζ above 1 gives a sluggish, overdamped approach to lock.
The first-order filter is a simple proportional gain, which leaves a small residual steady-state phase error under a frequency offset. The PI (proportional-integral) filter adds integral action, which drives steady-state phase error to zero once locked — this is why most practical PLLs use a PI filter. The lag-lead filter is a pole-zero design that shapes the loop's frequency response similarly to the PI filter but is expressed as a discrete pole-zero pair; the Bode plot updates live so you can compare their magnitude responses directly.
The loop is flagged as LOCKED once the phase error stays below a small threshold (0.1 rad) for 50 consecutive samples; it drops back to ACQUIRING if the error later exceeds three times that threshold. Pull-in range (shown as ± radians in the stats panel) is estimated from the product of VCO gain K₀ and phase detector gain Kd — it represents the maximum initial phase offset the loop can be expected to acquire from, given its current gain settings.
PLLs are one of the most common building blocks in electronics. Clock generation and frequency synthesis circuits use a PLL to multiply a stable low-frequency crystal reference up to the multi-gigahertz clock speeds modern processors need. Digital receivers use PLL-based clock and data recovery (CDR) circuits to re-derive a clean bit clock from a noisy incoming data stream. FM radio demodulators use a PLL to track the carrier's instantaneous phase and recover the audio signal, and GPS receivers use PLLs to lock onto each satellite's carrier frequency for precise ranging.