A phase-locked loop (PLL) is a feedback control system that forces an internal oscillator to track the frequency and phase of an incoming reference signal. PLLs sit inside almost every clock recovery circuit, radio receiver, frequency synthesizer and motor controller. This scene shows the classic three-block PLL: a phase detector that compares reference and feedback edges, a loop filter that smooths the error into a control voltage, and a voltage-controlled oscillator (VCO) whose frequency shifts with that voltage.
PLLs were first analyzed rigorously by Henri de Bellescize in 1932 for synchronous radio reception. Today a single modern smartphone SoC can contain dozens of PLLs, each synthesizing a different clock frequency from one master crystal reference.
A 3D block diagram of a phase-locked loop — reference oscillator, phase detector, loop filter and voltage-controlled oscillator — where detuning the reference in frequency or phase shows the feedback loop pulling the VCO back into lock.
The phase detector measures the angular gap between the reference and VCO spinner markers; the loop filter integrates that error into a control voltage; the VCO's spin rate follows the voltage until the phase error collapses to a steady offset — the definition of "locked."
Detune the reference frequency or jump its phase and watch the loop re-acquire lock. Widen the loop filter bandwidth for faster but noisier tracking, or add reference noise to see the filter's smoothing at work. Use the kick button for a step-response transient.
Modern chips can pack dozens of PLLs on one die, each synthesizing a different clock rate from a single master crystal reference — the same lock-and-track principle shown here, just at gigahertz speeds.