The plant is a 30-stage serial line of finite-buffer stations. Kits (24 blocks) arrive as a Poisson stream with mean gap Ta; each station serves batches of size b with deterministic cycle time s, plus random breakdowns (exponential time to failure with mean MTBF, exponential repair with mean MTTR). Stations are FCFS and a full buffer rejects the kit.
Utilisation law: busy fraction ρ = X·s·(1 + MTTR/MTBF) / (b·c) for throughput X and c parallel servers. Little’s law: L = λ·W, mean kits in the plant equals the accepted arrival rate times the mean time in plant. Both are checked against the simulation output. Batch stations (kiln, cure buffer, tumbler, mixer, dryer) release kits in bursts, which is why a lightly loaded station downstream can still overflow.
The engine is the same discrete-event model as the 3D page (event heap, seeded PRNG). Figures are illustrative engineering scenarios, not measured data from any real factory; AGV contention is not modelled; the floor plan uses the machine positions of the 3D layout.