This 2D top-down companion to the 3D single-wire QCA sim shows the structure a straight wire cannot: a majority gate, where three input wires physically converge in the plane on one shared cell. Each cell still holds two mobile electrons on a bistable diagonal,
P = (ρ13 − ρ24) / (ρ13 + ρ24) ∈ [−1, +1]
and is driven by the same 4-phase adiabatic clock as the 3D wire — Switch → Hold → Release → Relax, offset 90° zone to zone:
c(t) = ½(1 + cos(2π(t/T − k/4))) barrier height, zone k = 0..3
wire cell: dP/dt = R·(1−c)·(tanh(β·P_prev) − P)
gate cell: dP/dt = R·(1−c)·(tanh(β·(P_A+P_B+P_C)) − P)
The only physics that differs from a plain wire is what feeds the tanh: an ordinary clocked cell relaxes toward the field of its single upstream neighbor, but the gate cell's kink energy sums the fields of three neighbors at once. Because each input settles near ±1 (a clean bit), the sign of that sum is always well defined — for three ±1 inputs the sum can only be ±1 or ±3, never zero — so the gate cell locks onto sign(A+B+C): true majority voting, computed the same way real QCA majority gates (Lent & Tougaw, 1990s–2000s) do it, purely electrostatically and with no transistors.
- Flip A / B / C — toggle each of the three fixed driver cells feeding the gate.
- Clock period — slower clocking gives each zone more time to relax fully onto its neighbors' field before latching; faster clocking can outrun the relaxation rate and blur the pipeline.
- Output wire — after the gate cell, the majority result cascades down five more clocked cells exactly like the 3D wire, one zone per quarter cycle.
Because a 3-input convergence only makes geometric sense drawn in-plane, this 2D view demonstrates a genuinely different QCA building block than the 3D sim's straight adiabatic wire — the majority gate (with fixed inputs at 1 or −1) is also how QCA implements AND and OR gates, making it the universal logic primitive of the technology.