This is the 2D companion to the 3D Cryostat Wiring Bottleneck simulator. Instead of reading conducted heat per line from a fixed lookup table, this version derives it independently for each of the four stage-to-stage wire segments (300K→4K, 4K→Still, Still→CP, CP→MXC) from a real material thermal-conductivity model k(T), numerically integrated stage by stage:
Q_wire = (A/L) · ∫[T_cold, T_hot] k(T) dT (Simpson's rule, 200 intervals)
k_steel(T) ≈ 0.30 + 0.048·T [W/m·K]
k_NbTi(T) ≈ 0.0008·T³ for T < 9.2 K (superconducting phonon-only conduction)
= k_steel(T) for T ≥ 9.2 K (normal-state NbTi)
Below its critical temperature NbTi's electrons condense into Cooper pairs and stop carrying heat, leaving only a weak lattice-phonon channel that falls off steeply with temperature (T³ Debye-like scaling) — which is why the ratio between the two materials' conducted heat grows from ~1× at 4 K (segment unaffected — the 300K→4K run is always ordinary metal) to over a million-to-one by the time the wire reaches the mixing chamber.
Each stage segment's conducted load per wire scales exactly linearly with the number of lines threading it and inversely with the physical wire length between stages — both verified numerically before shipping this model. The mixing chamber's heat budget then sets its equilibrium temperature the same way real dilution units behave (cooling power ∝ T²):
T_MXC = T₀ · √(max(1, Q_load / Q₀)), T₀ = 10 mK, Q₀ = 20 µW
n̄(T) = 1 / (exp(hf / k_BT) − 1), f = 5 GHz qubit frequency
- Qubit count / lines per qubit — sets the total coax line count threading every segment of the fridge.
- Stainless steel vs. NbTi — swaps which k(T) model governs the three segments below 4 K.
- Freq-mux readout — cuts effective line count ~60%, modelling shared readout lines.
The ladder diagram shows every segment's load-to-budget ratio directly (green→amber→red); the lower curve plots the real Bose–Einstein thermal-photon occupation across a temperature sweep with the current operating point marked, so you can see exactly how far into the decoherence-inducing regime a given wiring choice pushes the chip.