A single long ion chain does not scale: as more ions share one trap, laser addressing and mode spectra get crowded. The QCCD (Quantum Charge-Coupled Device) architecture — proposed by Kielpinski, Monroe & Wineland (2002) — solves this by keeping only a couple of ions in any one trapping region. Idle qubits sit in separate memory zones; when a two-qubit gate is needed, the segmented trap's DC electrodes ramp their voltages in sequence — exactly like shifting charge through a CCD register, hence the name — to drag the selected ions along the axis into a shared gate zone, perform the entangling gate, then shuttle them home.
Adiabaticity: fast transport (T ≲ 1/ω_trap) is diabatic → excites motion
Heating/shuttle: Δn̄ ≈ K / T² (smooth "minimum-jerk" voltage ramp)
Idle cooling: n̄(t) = n̄₀ · e^(-γt) (sympathetic cooling, applied continuously here)
Gate fidelity: F ≈ F_max · e^(-n̄ / n_crit)
- Shuttle time T — how long the voltage ramp takes. Short T is fast but diabatic, so it dumps more motional quanta (Δn̄ ∝ 1/T²) into the ion; long T is slow but nearly adiabatic. Each full cycle shuttles the pair in, performs the gate, and shuttles them back out — three separate heating events at this same rate.
- Cooling rate γ — how quickly a Doppler/sympathetic-cooling beam removes accumulated motional quanta, identical to the 3D source's formula.
- Memory zones — how many separate storage regions feed the one shared gate zone; every cycle picks two zones at random and reunites their qubits for a gate, then splits them apart again.
- The highlighted electrode segment under each moving ion shows which DC electrode currently holds the confining potential — the "moving well" that physically carries the ion, the mechanism that gives the architecture its name. Scroll to zoom and drag to pan along the trap axis.
This is the scaling strategy behind IonQ's and Quantinuum's (Honeywell) commercial trapped-ion processors — physically re-wiring qubit connectivity by moving the qubits themselves, instead of routing gates through a fixed chip layout as superconducting processors must.