Squeezing usable signal out of noisy intermediate-scale quantum processors — zero-noise extrapolation, probabilistic error cancellation, readout calibration, and dynamical decoupling, without full fault-tolerant error correction
Noisy Intermediate-Scale Quantum (NISQ, a term coined by John Preskill in 2018) processors run real algorithms on real, imperfect hardware — typically 50 to about 1,100 physical qubits with no error correction protecting the computation. Every gate, every idle moment, and every measurement injects error. Understanding the physical origin of that error is the prerequisite for deciding which mitigation technique actually addresses it.
Three independent error channels compound on every circuit execution:
1. Decoherence (T1, T2): • T1 (energy relaxation time): mean time for |1⟩ to spontaneously decay to |0⟩ via coupling to the environment (phonons, quasiparticles, TLS defects in superconducting qubits) • T2 (dephasing time, T2 ≤ 2T1): mean time before relative phase information between |0⟩ and |1⟩ is scrambled by low-frequency noise (flux noise, charge noise) • Superconducting transmons (IBM, Google): T1, T2 typically 100–300µs on current-generation chips • Trapped ions (IonQ, Quantinuum): T2 can reach seconds to minutes — orders of magnitude longer, but gate operations are also slower (µs vs ns), so the effective error-per-gate-time ratio is what matters
2. Gate infidelity: • Single-qubit gate error: ~0.01–0.05% on leading superconducting platforms (microwave-driven rotations) • Two-qubit gate error dominates the budget: 0.1–1% typical for CNOT/CZ/ECR gates, because entangling gates require precise, longer pulses that are more sensitive to control noise, crosstalk, and leakage to non-computational states (e.g., the transmon |2⟩ level) • Circuit fidelity falls roughly as (1-ε)^(N_2Q) — a 100-CNOT circuit at ε=0.5% survives with only ~60% fidelity from 2Q gates alone, before readout or decoherence
3. Crosstalk and correlated error: • Frequency-crowded superconducting lattices suffer ZZ-coupling: always-on residual interaction between neighboring qubits causes conditional phase accumulation even when no gate is being applied • Simultaneous gate operations on nearby qubits can interfere via shared control lines or resonators — measured as non-Markovian, spatially correlated error that simple depolarizing-channel models underestimate • Characterized via simultaneous randomized benchmarking (RB) and cross-entropy benchmarking (XEB), the latter used by Google to certify quantum supremacy/advantage claims
Google's Willow chip (Dec 2024, 105 qubits) demonstrated below-threshold surface-code scaling for the first time — logical error rate per cycle dropped from 3.028% (distance-3) to 1.474% (distance-5) to 0.143% (distance-7), the key experimental proof that adding more physical qubits to a code can suppress error exponentially rather than add noise, validating the fault-tolerance roadmap this simulation contrasts against NISQ mitigation.
ZNE (Temme, Bravyi & Gambetta, 2017; Li & Benjamin, 2017; deployed at scale by IBM as part of Qiskit Runtime's resilience levels) is the most widely deployed error-mitigation technique on today's cloud quantum hardware precisely because it requires no extra qubits and no detailed noise model — only the ability to run the same logical circuit at several artificially inflated noise strengths and fit a curve back to zero.
Step 1 — Amplify noise without changing the logical circuit:
• Unitary/gate folding: replace each two-qubit gate G with G·G†·G (identity in the noiseless limit, but three times the physical noise exposure) — giving effective scale factor λ=3 for whole-circuit folding, or apply it to a random subset of gates for fractional λ • Pulse stretching: on platforms with pulse-level access (Qiskit Pulse), stretch the duration of control pulses by a factor λ, which proportionally increases the decoherence exposure per gate without altering the intended unitary • Digital gate insertion: insert pairs of identity-equivalent gates (e.g., X·X) that are logically trivial but each carry the platform's native gate error
Step 2 — Measure the observable at each noise level: • Run the circuit at λ = 1, 1.5, 2, 2.5, 3 (or similar), each with enough shots (typically 1,000–10,000) to bound statistical error below the expected mitigation gain • Record ⟨O⟩(λ) — the noisy expectation value of the observable of interest at each scale factor
Step 3 — Extrapolate to λ=0: • Linear fit: ⟨O⟩(λ) ≈ a + bλ → zero-noise estimate = a. Works well when noise is weak and error scales linearly • Richardson extrapolation (polynomial): fits a degree-(n-1) polynomial through n data points, exactly cancelling noise-order terms up to (n-1) — more accurate for stronger noise but more sensitive to shot noise • Exponential fit: ⟨O⟩(λ) ≈ A + B·e^(-λ/λ0), often the best physical match to decoherence-dominated error, used in IBM's default resilience settings
Why it works despite not modeling the noise explicitly: • Under fairly general noise assumptions (Markovian, weak enough that a Taylor expansion around λ=0 is valid), the mitigated estimate's bias is provably reduced from O(ε) to O(ε^n) for an n-point extrapolation, at the price of a variance increase from repeated sampling • Because it needs no tomography of the actual noise channel, ZNE degrades gracefully rather than catastrophically when the noise model assumption is imperfect — the main reason it is the default mitigation level on IBM Quantum's cloud service today
PEC (Temme, Bravyi & Gambetta 2017; Endo, Benjamin & Yuan 2018) goes further than ZNE: instead of extrapolating a trend, it uses an explicit, tomographically characterized noise model to construct a signed (quasi-probability) mixture of physically realizable noisy circuits whose expectation value is, in exact expectation, identical to the noiseless circuit. It is unbiased in principle — the cost is paid entirely in sampling overhead, which grows exponentially with circuit size.
Core idea — represent the ideal gate as a signed combination of noisy, implementable ones:
G_ideal = Σ_i q_i · O_i, where Σ_i q_i = 1 but individual q_i may be negative
• O_i are quantum operations that CAN actually be run on the noisy hardware (e.g., the noisy native gate composed with Pauli twirls) • The q_i coefficients are found by inverting the characterized noise channel (via gate set tomography, GST) for that specific gate on that specific qubit pair • γ = Σ_i |q_i| ≥ 1 quantifies "how hard" the noise is to invert — γ=1 means noiseless, γ→∞ means inversion requires huge cancellation between positive and negative terms
Sampling procedure: 1. For each noisy gate in the circuit, sample O_i from the distribution |q_i|/γ_gate 2. Run the resulting physical circuit, record the measurement outcome, multiply by the accumulated sign sign(q_i) and normalize by γ_gate for every gate sampled 3. Repeat many times (Monte Carlo); the sample mean converges to the exact noiseless expectation value: ⟨O⟩_ideal = γ_total · E[sign-weighted noisy outcome]
Why the overhead is exponential: • Total γ_total = Π_gates γ_gate — even a modest per-gate γ_gate=1.05 compounds multiplicatively across n gates • Required sample count to reach a target statistical precision scales as C(γ) = γ_total², i.e. roughly γ^(2n) — for realistic NISQ gate error rates this becomes impractical beyond a few dozen two-qubit gates • This is the fundamental reason PEC, despite being the more rigorous mitigation technique, sees far less production deployment than ZNE: its cost curve crosses "impractical" earlier as circuits scale
Practical hybrid use: • PEC is typically reserved for small, high-value subcircuits (e.g., a single noisy two-qubit gate layer in an otherwise well-characterized circuit) rather than applied end-to-end • Combined approaches (PEC for the worst gates, ZNE for the rest) are an active area of Qiskit Runtime and Mitiq (open-source mitigation library, Unitary Fund) research as of 2024–2025
Two more error sources sit outside the gate-error picture entirely: the measurement/readout process itself (state discrimination error of 1-3% per qubit on superconducting hardware) and dephasing accumulated while a qubit sits idle waiting for other parts of the circuit to finish. Both have cheap, well-established mitigations that are frequently applied together with ZNE or PEC as part of a standard mitigation stack.
Readout error mitigation:
1. Calibration step: prepare each of the 2^n computational basis states |00...0⟩ through |11...1⟩ (for practical n, only a subset or a tensor-product approximation is calibrated), measure each many times, and record the resulting confusion matrix M where M_ij = P(measure j | prepared i) 2. Correction step: given a raw measured probability vector p_noisy over bitstrings, solve p_ideal = M⁻¹ · p_noisy • Direct inversion is exact but can produce small negative "probabilities" from statistical noise, and M is 2^n × 2^n — intractable to build or invert directly beyond ~15-20 qubits • Practical libraries (Qiskit's M3 — Matrix-free Measurement Mitigation, Nation et al. 2021) exploit the fact that readout error is nearly local (per-qubit) to build a reduced, iterative correction that scales linearly rather than exponentially, and constrain the solution to a valid probability simplex
Dynamical decoupling (DD) for idle qubits:
• Problem: in any real circuit, most qubits spend much of the circuit depth idle, waiting for other qubits' gates — during this idle window they still accumulate dephasing from slow environmental noise (1/f flux/charge noise) • Solution: insert sequences of otherwise-identity pulse pairs (e.g., X-X, or the more robust XY4 = X-Y-X-Y, or CPMG = π-pulse trains) into idle windows • Mechanism: each decoupling pulse flips the qubit's interaction sign with slowly-varying environmental noise; over the full sequence the accumulated phase error partially cancels — a direct descendant of Hahn spin-echo (1950) and Carr-Purcell-Meiboom-Gill NMR sequences, adapted to gate-model quantum circuits • Uhrig dynamical decoupling (UDD, 2007) uses non-uniformly spaced pulses, provably optimal for certain noise spectra (1/f-dominated) • Practical effect: on circuits with significant idle time (common in wide, shallow circuits), DD insertion measurably improves fidelity — IBM Qiskit's transpiler includes a `PadDynamicalDecoupling` pass to automate this
Both techniques are essentially free in qubit count and are typically combined as a baseline layer beneath ZNE or PEC, which then handle the residual gate-level coherent and incoherent error.
Error mitigation techniques reduce the bias of an expectation value estimated from noisy hardware — they do not correct errors mid-computation, they do not reduce the physical error rate, and their sampling overhead grows (often exponentially) with circuit size. Quantum error correction (QEC) is fundamentally different: it encodes one logical qubit redundantly across many physical qubits so that errors can be detected and corrected during the computation, enabling circuits of unbounded depth — but at an enormous current qubit-count cost.
Error mitigation (this simulation's subject): • Operates entirely in post-processing / repeated sampling on the SAME small number of physical qubits • No redundant encoding — a "logical qubit" and a "physical qubit" are the same object • Reduces bias in expectation values of observables; does NOT reduce the error rate of the underlying quantum state during the computation • Overhead: polynomial (ZNE) to exponential (PEC) in circuit depth/error rate — becomes impractical for large, deep circuits • Deployable TODAY on 50-1,100 qubit NISQ devices with zero additional hardware
Quantum error correction (the long-term target): • Encodes 1 logical qubit across many physical qubits (e.g., a distance-d surface code uses roughly d² physical qubits per logical qubit) • Continuously measures syndrome qubits (without collapsing the encoded logical state) to detect and actively correct errors DURING the computation • Below a hardware-dependent threshold physical error rate (~1% for the surface code with realistic noise), increasing code distance d exponentially suppresses the logical error rate — Google's Willow (Dec 2024) was the first experimental demonstration of this scaling crossing below threshold, more than a decade after the surface code threshold theorem • Enables circuits of arbitrary depth — the prerequisite for algorithms like Shor's factoring or large-scale quantum chemistry simulation that require millions of coherent gate operations
Current hardware landscape (2025-era, illustrative): • IBM Heron r2: ~133-156 qubits per chip, tunable couplers, 2Q error ~0.3%, designed for modular scaling via quantum-classical "Crossbill"/"Kookaburra" interconnects toward 2029 fault-tolerant roadmap targets • IBM Condor (2023): 1,121 physical qubits, largest single superconducting chip demonstrated, still fully NISQ (no logical qubits) • Google Willow: 105 qubits, first below-threshold surface-code logical qubit demonstration • IonQ Forte / Quantinuum H2: trapped-ion, ~32-56 algorithmic qubits but very high two-qubit fidelity (>99.9%) and all-to-all connectivity • None of these devices today run a single logical qubit with practically useful error rates in a general-purpose way — estimates for a cryptographically relevant fault-tolerant machine (e.g., breaking RSA-2048 via Shor's algorithm) still call for on the order of 1 million physical qubits (Gidney & Ekerå, 2021), underscoring why mitigation — not correction — is the pragmatic tool for extracting value from quantum hardware through the rest of this decade.
The honest framing: NISQ error mitigation buys time and extracts genuine scientific and algorithmic value from today's imperfect hardware, but it is explicitly a bridge technology. Every serious hardware roadmap (IBM, Google, Quantinuum, PsiQuantum) treats fault-tolerant QEC — not better mitigation — as the actual path to large-scale quantum advantage; mitigation's exponential sampling overhead is the mathematical reason it cannot substitute for correction at scale.