An n-channel MOSFET (metal-oxide-semiconductor field-effect transistor) controls a current between two n+ terminals — the source and drain — embedded in a p-type silicon substrate. A voltage applied to the gate, insulated from the body by a thin oxide layer, attracts electrons to the surface and forms a thin conducting inversion channel once it exceeds the threshold voltage Vth. The 3D model here shows that channel forming, narrowing toward pinch-off near the drain, and the resulting current sweeping out the classic MOSFET I-V curve.
Modern CPUs pack tens of billions of MOSFETs with channel lengths under 5 nanometers — only a few dozen silicon atoms wide — yet the same square-law equations discovered for centimeter-scale devices in the 1960s still describe their basic switching behaviour.
A 3D cutaway of an n-channel MOSFET shows the inversion channel forming, thinning toward pinch-off, and the electron flow that follows — while a live current-voltage graph traces the transistor through cutoff, triode, and saturation.
How gate-source voltage sets the channel's inversion charge, how drain-source voltage drives current through it, and how those two voltages together define which of the three MOSFET operating regions the device sits in.
Drag the VGS, VDS, and Vth sliders and watch the channel, depletion wedge, and electron flow respond in the 3D model, or press Auto-sweep to trace the full I-V curve automatically.
The same square-law I-V equations used here, formalized in the 1960s, still describe the basic switching behaviour of the tens of billions of MOSFETs packed into a modern CPU die.