Watch the VCO track the input signal
A phase-locked loop (PLL) is a feedback system that makes a local oscillator match the frequency and phase of an incoming signal. Here you can watch the input waveform (blue) and the VCO waveform (orange) drift apart, then converge as the loop acquires lock — and step the input frequency to watch it re-lock.
sin(θ_err).θ_err = θ_in − θ_vco
v_pd = sin(θ_err)
v_ctrl += (v_pd·K − v_ctrl)·BW·dt
f_vco = f_centre + v_ctrl
The PLL was invented by Henri de Bellescize in 1932 for synchronous AM radio reception. Today a single CPU may contain dozens of PLLs generating and aligning its clock signals.
What is a phase-locked loop (PLL)?
A PLL is a feedback control system that makes a local oscillator track the frequency and phase of an incoming reference signal. It contains a phase detector, a loop filter and a voltage-controlled oscillator (VCO).
What does the phase detector do?
The phase detector compares the input signal with the VCO output and produces an error voltage proportional to the phase difference between them. In this simulation it is modelled as a multiplier whose low-frequency component is proportional to the sine of the phase error.
What is the role of the loop filter?
The loop filter is a low-pass filter that smooths the phase-detector output, removing high-frequency components and noise so that only the slowly varying control voltage drives the VCO. Its bandwidth sets the loop's speed and stability.
A voltage-controlled oscillator generates a periodic signal whose frequency depends on its input control voltage. The PLL adjusts that voltage until the VCO frequency and phase match the input reference.
The capture range is the band of input frequencies over which an unlocked PLL can acquire lock. The lock (hold) range is the wider band over which an already-locked PLL stays locked. The lock range is generally larger than the capture range.
In a first-order loop, a constant steady-state phase error is needed to produce the control voltage that keeps the VCO at the input frequency. The larger the frequency offset, the larger the steady-state phase error required.
A sudden change in input frequency creates a growing phase error. The loop responds by changing the VCO frequency to chase the new input, and after a transient the phase error settles again — this is re-locking.
Higher loop gain widens the capture and lock ranges and speeds acquisition but can cause overshoot or ringing. A wider filter bandwidth makes the loop faster but lets more noise through; a narrower bandwidth is cleaner but slower.
PLLs are everywhere: FM radio demodulators, clock recovery in data links, frequency synthesizers in radios and CPUs, tone decoders, and motor speed control. Almost every modern radio and digital chip relies on them.
It is a faithful behavioural model of a first-order analog PLL using a multiplier phase detector, an RC-style low-pass loop filter and a sinusoidal VCO. It captures lock, re-lock, capture/hold range and the gain/bandwidth trade-offs without simulating transistor-level circuitry.