A nanocapacitor is a parallel-plate metal–insulator–metal (MIM) stack scaled down so far that the dielectric is only a handful of atomic layers thick. Two effects then compete directly:
Capacitance density: C/A = ε₀εr / d
Equivalent oxide
thickness (EOT): EOT = d · (3.9 / εr)
WKB tunneling
current density: J ≈ J₀·V·exp(−2κd), κ = √(2m*qφB) / ħ
Shrinking d raises C/A, but the same exponential in the tunneling formula means leakage current explodes even faster — a bare atomic layer or two of silicon dioxide leaks orders of magnitude more than the same capacitance built from a thicker high-κ film. Swapping in HfO₂, ZrO₂ or TiO₂ (κ up to ~25–80 vs 3.9 for SiO₂) lets the physical film stay thick enough to block tunneling while the equivalent oxide thickness — and hence the capacitance an engineer actually gets — stays sub-nanometer. This is exactly the trade-off that forced DRAM and logic-transistor gate stacks off pure SiO₂ once nodes passed roughly 2 nm of oxide.
- Dielectric dropdown — swaps εr and the tunneling barrier height φB used by both formulas above; the slab color and the barrier readout update immediately.
- Thickness slider — the physical film thickness d, 0.5–5 nm; the visual gap between the plates scales with it.
- Voltage slider — the bias V across the film; charge dots on the plate faces and the field arrows scale with it, and J is linear in V in this low-field WKB model.
- Tunneling electrons — toggles the animated particles hopping from the bottom electrode to the top one; their emission rate is driven by the computed J, so a leakier setting visibly floods the gap while a well-insulated one shows only the occasional electron.
The prefactor J₀ and effective mass m* = 0.4·mₑ are fixed, illustrative constants shared across all six materials — only εr, φB and d change per selection — so the simulator isolates the real trade-off (capacitance vs. leakage vs. material) rather than fitting any single fabrication process.