Moore's Law — 2D Die Scaling Simulator

Timeline

Year 1971

Playback speed 6 yr/s

Doubling period 24 mo

Live Readouts

Transistors / chip

2,300

Feature size

10,000 nm

Density

0.2 M / mm²

How it works

Moore's Law (1965/1975) observes that the number of transistors economically packed on a chip roughly doubles every fixed period T (historically ≈ 18–24 months):

N(t) = N0 · 2^((t − t0) / T)

N0 = 2,300   (Intel 4004, 1971)
t0 = 1971
T  = doubling period, yr

Doubling the transistor count in the same die area means each transistor's linear "feature size" f must shrink so its footprint (∝ f²) halves — i.e. f shrinks by √2 every T, or by ×2 every 2T:

f(t) = f0 · 2^(−(t − t0) / (2T))

f0 = 10,000 nm (10 µm, 1971 process node)

The flat grid you see is a fixed-size patch of die viewed top-down: every doubling period it subdivides into finer cells, each cell one simulated transistor. Areal density follows directly: density = N(t) / die_area. By the 2000s this shrink pushes feature size below 100 nm — into the nanoscale regime where quantum tunneling, atomic-layer deposition and scanning-probe metrology (the tools nanotechnology brought to the fab) become unavoidable engineering constraints rather than curiosities.

Year slider / Play — scrub or animate the timeline; the grid resolution and cell size update live from the formulas above.
Doubling period — test a faster or slower Moore's Law (12–36 months) and see how it changes the 2035 transistor count.
Drag to pan, scroll to zoom into the die — useful once the grid is too fine to read at full extent.
Reset — back to the 1971 starting point (Intel 4004: 2,300 transistors, 10 µm process). Reset view — recenters pan/zoom.

1971

Drag to pan · Scroll to zoom

Active transistor cell Die substrate