Nanowire Transistor Quantum Confinement

Nanowire Channel

Diameter D 8.0 nm

Channel material

Gate Bias

Gate voltage V_G 0.30 V

Temperature T 300 K

Readouts

1st subband E₁

— meV

Threshold V_th

— V

Drain current I_D (relative)

—

Subband occupation

E₁

— meV

E₂

— meV

E₃

— meV

How it works

A gate-all-around nanowire confines electrons in a cylinder of radius R. Treating the channel as an infinite circular well gives quantized radial subbands from the zeros of the Bessel function J_l:

E_l,n = ħ² α_l,n² / (2 m* R²)
α_01 = 2.405   (1st subband, l=0)
α_11 = 3.832   (2nd subband, l=±1)
α_02 = 5.520   (3rd subband, l=0)

Because E ∝ 1/R², shrinking the wire pushes the lowest subband up in energy — the gate has to work harder to pull it down to the source Fermi level before current can flow. That extra gate voltage is modeled here as a threshold-voltage shift:

V_th(D) = V_th0 + E₁(D) / q
I_D ∝ exp[(V_G − V_th) / (n·kT/q)]   below threshold (subthreshold leakage)
I_D ∝ (V_G − V_th)²                   above threshold (square-law MOSFET)

Diameter — smaller D raises every subband energy and V_th; watch the electrons in the channel thin out at a fixed gate voltage as you shrink the wire.
Material — a lighter effective mass (InAs) confines much more weakly than Si for the same diameter, since E₁ ∝ 1/m*.
Gate voltage — sweeps the channel from depleted (barrier, only leakage current) through threshold into strong inversion (full conduction); the conduction-band line bends down under the gate as V_G rises.
Temperature — sets the thermal energy kT that both smears the subthreshold turn-on and thermally populates higher subbands.

Real-world relevance: this radial-confinement threshold shift is exactly what limits how far gate-all-around silicon nanowire and nanosheet transistors — the leading device architecture beyond FinFETs at sub-3 nm process nodes — can be scaled down before V_th control and drive current collapse.

Gate-all-around shell Conduction electrons Conduction-band edge

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