CMOS Inverter: Voltage Transfer Characteristic & Switching Dynamics

Input & Supply

Input voltage V_in 0.60 V

Supply V_DD 1.20 V

Transistor Sizing

Width ratio W_p/W_n 2.20

Output Load

Load capacitance C_L 10 fF

Transient Switching

Live State

Output V_out

1.20 V

Channel current

0.0 µA

Transistor regions

NMOS: cutoffPMOS: sat

Last measured propagation delay

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How it works

A CMOS inverter stacks a PMOS pull-up (source at V_DD) on top of an NMOS pull-down (source at ground), gates tied together at V_in, drains tied together at V_out. Exactly one device conducts strongly at a time — that is why static CMOS burns almost no power when idle. Each transistor follows the long-channel square-law (Shichman–Hodges) model:

Cutoff (Vov ≤ 0):        I = 0
Triode (Vds < Vov):      I = k·(Vov·Vds − Vds²/2)
Saturation (Vds ≥ Vov):  I = (k/2)·Vov²
  where Vov = Vgs − Vt  (NMOS)  or  Vov = Vsg − |Vtp|  (PMOS)

For a given V_in, the simulator solves I_NMOS(V_out) = I_PMOS(V_out) numerically (bisection) — this traces the voltage transfer characteristic (VTC). The switching threshold V_M is set by the ratio k_p/k_n, which is why the W_p/W_n slider re-centers the curve: wider PMOS compensates for holes' lower mobility (~0.45× electrons here) and pulls V_M back toward V_DD/2.

Switching the input drives a transient: with V_in high, only the NMOS conducts and pulls the load capacitor down, C_L·dV_out/dt = −I_NMOS(V_out); with V_in low, only the PMOS conducts and charges it up, C_L·dV_out/dt = +I_PMOS(V_out). The propagation delay t_PHL / t_PLH reported is the real time for V_out to cross V_DD/2, integrated directly from that ODE (fast-forwarded for viewing, not the underlying physics) — this is the same RC-style delay model used to estimate real digital logic timing.

Holes (PMOS channel) Electrons (NMOS channel) V_out on VTC curve

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