The 3D scene solves a single lumped 0D current per transistor (I vs. Vout) by bisection and animates carriers riding a fixed sinusoidal path — it never resolves anything along the channel. This 2D simulator instead spatially resolves each device with the gradual-channel approximation (GCA): the channel potential V(x) between source (x=0) and drain (x=L) obeys
I·dx = k·(V_ov − V(x))·dV(x) [charge continuity along the channel]
⇒ V(x) = V_ov − √( V_ov² − 2·I·x / k )
Integrating this ODE (verified independently by Runge–Kutta stepping against the closed form below) gives the local inversion-charge density Qi(x) = k·(Vov − V(x)) at every point, not just the terminal current — that is what the tapering channel band actually plots. In saturation the profile reaches Vov exactly at the drain end (xp/L = 1, the idealized long-channel pinch-off), after which this model (like the 3D one) does not add channel-length modulation, so I stays a function of Vov alone.
A second, entirely new mechanism has no counterpart in the 3D scene at all: the drain–body pn junction is modeled as a one-sided step junction whose depletion width grows with reverse bias and shrinks with doping,
W(V_r) = W₀ / √(N_a/N_a0) · √(1 + V_r / V_bi), V_bi = 0.7 V
drawn as the dashed boundary eating into the drain diffusion. Because Vout sets the NMOS drain's reverse bias directly and VDD−Vout sets the PMOS drain's, this depletion width visibly breathes in and out as the inverter switches — a real electrostatic effect the 3D model's carrier animation cannot show because it has no notion of space at all.
- Width ratio Wp/Wn — same role as in the 3D scene: re-centers VM by scaling kp, which changes where each channel's charge profile pinches.
- Relative body doping Na — new here: higher doping compresses the depletion region (W ∝ 1/√Na), the same trade-off real process engineers make against latch-up and junction breakdown.