Metals and ceramics in engineering use are almost universally polycrystalline—composed of many small single-crystal grains, each with a different crystallographic orientation, separated by grain boundaries. During solidification, crystal nuclei form at many points simultaneously and grow until they impinge on each other, creating the grain boundary network. The resulting microstructure can be visualized using Voronoi tessellation: given a set of seed points (nucleation sites), each region of the Voronoi diagram contains all points closer to that seed than to any other—reproducing the geometry of solidification-generated grain structures remarkably well.
Grain boundaries are planar defects where two grains of different orientation meet. Low-angle grain boundaries (misorientation < ~15°) consist of ordered arrays of dislocations and have low energy. High-angle grain boundaries (misorientation > 15°) are more disordered and have higher energy (~0.5–1 J/m²). Special boundaries (coincidence site lattice boundaries, or CSL boundaries) where a fraction of atoms from both crystals coincide have particularly low energy and influence corrosion resistance, fracture behavior, and electromigration in semiconductor interconnects.
This simulator generates polycrystalline microstructures using Voronoi tessellation from randomly placed or regular seed arrays, colors grains by orientation angle, and highlights grain boundaries. You can vary the number of grains (nucleation density), display misorientation angles, apply simulated etching to reveal grain boundary contrast, and observe how grain size distribution follows a log-normal distribution—standard in metallography, materials characterization, and EBSD analysis.
What is the Voronoi tessellation and why does it model grain structures?
A Voronoi tessellation partitions space so that each cell contains all points closer to one seed than to any other seed—equivalent to equidistant boundaries between seeds. During solidification, crystal nuclei grow radially at equal rates until they meet growing neighbors; the boundaries between grains form exactly where two growth fronts were equidistant from their respective nuclei. Real grain structures match Voronoi tessellations well when nuclei activate simultaneously and growth rate is isotropic—assumptions that hold approximately for many casting and sintering processes.
How do you measure grain size experimentally?
ASTM grain size is measured by the intercept method: count how many grain boundaries a random line crosses per unit length (intercept density N_L), giving mean intercept length l = 1/N_L. The ASTM grain size number G is defined as n = 2^(G-1) grains per mm² at 100× magnification; larger G means smaller grains (G=10 is ~10 μm; G=3 is ~90 μm). Modern characterization uses Electron Backscatter Diffraction (EBSD) in a scanning electron microscope, which maps crystallographic orientation at each pixel with 50 nm resolution.
How do grain boundaries affect corrosion resistance?
Grain boundaries are chemically more reactive than grain interiors due to their higher energy, atomic disorder, and tendency to segregate solute atoms. Sensitization of austenitic stainless steels occurs when heating in the 450–850°C range causes chromium carbide precipitation at boundaries, depleting nearby chromium below 12%. Grain boundary engineering—increasing the fraction of special low-energy CSL boundaries—dramatically improves corrosion resistance by creating networks of low-energy boundaries that resist sensitization and intergranular attack.
Crystallographic texture (preferred orientation) describes the non-random distribution of grain orientations in a polycrystalline material. In rolled metal sheet, grains rotate to preferred orientations during deformation, creating rolling, transverse, and normal texture components. Strong texture makes properties highly direction-dependent (anisotropic): deep-drawing aluminum sheet needs specific texture for uniform deformation without earing; transformer core silicon steel needs grains aligned with the easy magnetic direction ({110}[001] Goss texture) to minimize hysteresis losses.
In semiconductor devices, grain boundaries act as recombination centers that capture minority carriers and reduce solar cell efficiency—why monocrystalline silicon solar cells outperform polycrystalline ones. In thin-film transistors, grain boundaries limit carrier mobility, affecting switching speed. In copper interconnects in integrated circuits, grain boundaries increase electrical resistivity and serve as fast diffusion paths for electromigration, a primary failure mode. Bamboo structures (single grain across the interconnect width) eliminate lateral grain boundaries and dramatically improve electromigration lifetime in narrow copper lines.