One bit of digital memory
Cross-coupled NOR gates. Pulse SET to store a 1, RESET to store a 0 — the loop remembers it after the input releases.
A flip-flop is the smallest unit of digital memory: a circuit that remembers a single bit. This simulation builds it up in three stages — a raw SR latch of cross-coupled NOR gates, a clocked gated D latch, and finally an edge-triggered master–slave D flip-flop. Watch logic levels propagate gate by gate, see Q and its complement Q̄ settle, and read the bit off a live timing diagram.
Q⁺ = S + R̄·Q (SR latch next-state)
NOR(a,b) = ¬(a ∨ b) (the cross-coupled gate)
Q⁺ = D (D flip-flop, sampled at the clock edge ↑)
tsu ≤ Δt ≤ −th → metastable
Metastability is a genuine physical hazard, not a textbook abstraction. If data changes within the setup/hold window the flip-flop can balance on a knife edge and take an unbounded time to resolve — early computers occasionally crashed from it. Engineers tame it with synchroniser chains of extra flip-flops that give the wobble time to settle.
A flip-flop is a bistable digital circuit that stores one bit of information. It has two stable states — 0 and 1 — and stays in whichever state it was last set to, even after the inputs return to rest. This memory of a single bit is the foundation of every register, counter and CPU.
An SR latch is built from two cross-coupled NOR (or NAND) gates: the output of each gate feeds back into the input of the other. This feedback creates two self-reinforcing stable states. Pulsing Set forces Q to 1, pulsing Reset forces Q to 0, and when both inputs return to 0 the loop holds the last value indefinitely.
A latch is level-sensitive: it follows its data input the whole time the enable or clock is high (transparent). A flip-flop is edge-triggered: it samples its data input only at the instant the clock transitions, then holds that value until the next edge. Edge triggering makes synchronous design predictable.
If both Set and Reset are asserted at the same time in a NOR latch, both outputs are driven to 0, so Q and Q-bar are no longer complementary. When both inputs are released simultaneously the latch enters an unpredictable race and can settle either way. This is why the S=R=1 combination is called forbidden or invalid.
D stands for Data (sometimes Delay). A D flip-flop copies whatever is on its D input to Q on the active clock edge. Because the captured value appears at the output one clock cycle later, it effectively delays the data by one cycle, which is why it is the natural building block of registers and pipelines.
A master-slave flip-flop chains two gated D latches driven by opposite clock phases. While the clock is low the master latch is transparent and tracks D; while the clock is high the slave latch becomes transparent and passes the master's stored value to the output. The handover at the edge means only the value present at the transition is captured.
Metastability is when a flip-flop's output hovers at an indeterminate level between 0 and 1 because the data changed too close to the clock edge. The internal feedback loop is balanced on a knife edge and may take an unpredictable time to resolve. It is a real, physical failure mode in digital systems, mitigated by synchroniser chains.
Setup time is the interval before the clock edge during which the data input must already be stable. Hold time is the interval after the edge during which it must remain stable. Violating either window can push the flip-flop into metastability or capture the wrong value, so timing analysis enforces both.
Every register, program counter, pipeline stage and cache line in a CPU is built from flip-flops. They give a processor its state — the memory of what happened on the previous clock cycle — and the synchronous clocking they provide is what lets billions of logic operations stay coordinated each second.
Yes. A NAND-based SR latch is the dual of the NOR version: it is active-low, so the inputs are S-bar and R-bar and the resting state is both inputs high. NAND is a universal gate, so an entire flip-flop — including the gated D and edge-triggered variants — can be built from NAND gates alone.