Flip-Flop: 2D Gate-Level Latch Simulator

Controls

Gate delays per second

Clock period

Data change before clock edge

Data toggle every n clocks

How it works

All gates update together every tick (unit propagation delay). Cross-coupled gates hold state:

SR latch (NOR): Q = NOR(R, Qb); Qb = NOR(S, Q)
D latch (NAND): Q = NAND(NAND(D,E), Qb); Qb = NAND(NAND(NOT D,E), Q)
D flip-flop: master latch (E = NOT CLK) then slave latch (E = CLK)

The flip-flop captures D on the rising edge. If D changes less than the setup time (about 3 ticks of master settling) before the edge, the old or new value may be captured, or the outputs glitch - a setup/hold violation. S=R=1 followed by release in the SR latch causes a race.

Q-

Q-bar-

Clock edges-

Last capture-

Status-