8-Bit Ripple-Carry Adder — 2D Gate Diagram

Operand A (bit 7 → bit 0)

Operand B (bit 7 → bit 0)

Propagation speed 50

Ready — toggle bits or press Random to add A + B.

Result

A (decimal)

B (decimal)

Sum — binary (9-bit incl. carry-out)

0 00000000

Sum (decimal)

Carry-out / overflow

How it works

Every stage is a real full adder built from three logic gates, computed exactly as digital hardware does it:

Sum = A ⊕ B ⊕ Cin (two chained XOR gates)
Cout = (A · B) + (Cin · (A ⊕ B)) (two AND gates feeding one OR gate)

Eight of these stages are cascaded so each stage's carry-out feeds the next stage's carry-in — a ripple-carry adder. That dependency is why the diagram animates the carry propagating stage by stage from bit 0 up to bit 7: stage n cannot know its correct output until stage n−1 has resolved, exactly like the real hardware's propagation delay. If the final carry-out (stage 7) is 1, the true sum needs a 9th bit — an overflow the panel flags directly.

Real-world relevance: ripple-carry chains like this form the arithmetic core of ALUs; the propagation delay shown here is the same effect that limits how fast a real adder circuit can run, which is why faster designs (carry-lookahead, carry-select) exist for wide adders.

Idle gate Evaluating Carry = 1 Resolved stage