The simulation compares two cores writing to adjacent variables packed on one cache line against the same variables padded onto separate lines, showing the resulting coherence traffic and latency difference, with an optional NUMA node placement layer added on top.
Toggle between packed and padded memory layouts and assign cores to the same or different NUMA nodes, then run the write workload to compare measured latency and coherence event counts between configurations.
Toggle for packed vs padded layout, NUMA node assignment per core, run/measure button with latency readout
Padding a single 4-byte counter out to a full 64-byte cache line wastes 60 bytes of memory per counter, yet this deliberate waste can make heavily contended multithreaded code run several times faster.
The simulation compares two cores writing to adjacent variables packed on one cache line against the same variables padded onto separate lines, showing the resulting coherence traffic and latency difference, with an optional NUMA node placement layer added on top.
The simulation compares two cores writing to adjacent variables packed on one cache line against the same variables padded onto separate lines, showing the resulting coherence traffic and latency difference, with an optional NUMA node placement layer added on top.
Toggle between packed and padded memory layouts and assign cores to the same or different NUMA nodes, then run the write workload to compare measured latency and coherence event counts between configurations.
Padding a single 4-byte counter out to a full 64-byte cache line wastes 60 bytes of memory per counter, yet this deliberate waste can make heavily contended multithreaded code run several times faster.