Each of the 343 neurons on the 3D lattice is a leaky integrate-and-fire (LIF) unit — the same abstraction used by IBM TrueNorth and Intel Loihi 2's digital "neurosynaptic cores".
dV/dt = I(t) − leak · V
if V ≥ V_th: spike, V → 0, refractory
E_event ≈ n_spikes · e_spike
E_clocked ≈ N_total · e_tick (every tick, regardless of activity)
- Input stimulus rate — background Poisson-like drive current injected into every neuron, like a sensor feeding the chip.
- Firing threshold — membrane voltage V_th a neuron must reach before it spikes.
- Membrane leak — how fast unspiked voltage decays back toward rest; higher leak needs tighter-in-time input to trigger a spike.
- Synaptic connectivity — average number of outgoing synapses per neuron; a spiking neuron injects weighted current into its neighbours, which is how activity propagates through the lattice without a global clock.
- Event-driven / Clocked — toggles the energy-accounting model: event-driven only "spends" when a neuron actually spikes (its edges flash), clocked pays a fixed cost for every neuron every step — the core reason brain-inspired chips use orders of magnitude less power than a synchronous processor evaluating a dense network.
Real-world relevance: Intel's Loihi 2 and IBM's TrueNorth chips implement exactly this event-driven, asynchronous spiking model in silicon, achieving very low energy-per-inference for sparse, temporally-structured workloads like sensor processing and robotics.