The simulation shows several CPU cores sharing one memory address, with each core's cache line visibly transitioning between Modified, Exclusive, Shared, and Invalid states as bus read and write transactions are snooped.
Trigger a read or write from any core using the per-core controls and watch the resulting bus transaction propagate, invalidating or updating other cores' cache line states accordingly.
Per-core read/write buttons plus a reset control, with a bus transaction log panel
A cache line ping-ponging between two cores' Modified states on every write, known as false sharing when the variables are unrelated, can slow a multithreaded program down by 10x or more without producing a single incorrect result.
The simulation shows several CPU cores sharing one memory address, with each core's cache line visibly transitioning between Modified, Exclusive, Shared, and Invalid states as bus read and write transactions are snooped.
The simulation shows several CPU cores sharing one memory address, with each core's cache line visibly transitioning between Modified, Exclusive, Shared, and Invalid states as bus read and write transactions are snooped.
Trigger a read or write from any core using the per-core controls and watch the resulting bus transaction propagate, invalidating or updating other cores' cache line states accordingly.
A cache line ping-ponging between two cores' Modified states on every write, known as false sharing when the variables are unrelated, can slow a multithreaded program down by 10x or more without producing a single incorrect result.