Systolic Array Matrix Multiplier

Array Configuration

Array size N × N 5 × 5

Clock speed 1.5 cyc/s

Live Readouts

Clock cycle

0 / 0

Utilization

MACs computed

0 / 0

How it works

This is the core dataflow inside every matrix-multiply engine in modern AI hardware — Google's TPU MXU, NVIDIA's Tensor Cores, and dedicated ASICs like Gaudi3 or MI300X's matrix units. Instead of reading every operand from memory for every multiply, values are loaded once and pumped through a 2D grid of processing elements (PEs), each doing one multiply-accumulate (MAC) per clock tick.

C = A × B,  A,B,C are N×N

PE(i,j) accumulates:
  C[i][j] += Σ A[i][k]·B[k][j]

Skewed timing: PE(i,j) fires at cycle
  t = i + j + k,  for k = 0..N-1

So a diagonal wavefront of active PEs
sweeps across the array as k advances.

N × N — array size; more PEs means more parallel MACs per cycle but the array must be physically laid out on the chip die.
Clock speed — how fast the simulated clock advances (illustrative; real MXUs run at GHz).
Cube height / brightness — each PE's running accumulator |C[i][j]|, normalized to the largest current value.
Bright rim — PEs actively computing a MAC this cycle: a diagonal band that sweeps from the top-left corner to the bottom-right corner.
Total latency to drain the array is 3N−2 cycles, but once full, the array retires N² MACs every single cycle — this reuse of loaded operands across many MACs is exactly why systolic arrays are so energy-efficient per FLOP compared to a general-purpose CPU core, and why AI accelerators dedicate huge chip area to them.

Accumulator |C[i][j]| Active PE this cycle Streaming operand

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