Single-Event Upset: Cosmic Ray Bit Flips

Incoming Particle

Linear energy transfer (LET) 15 MeV·cm²/mg

Particle flux 4 /s

Spacecraft Memory

Critical charge Q_crit 12 fC

Aluminum shielding 0 mm

Live Readout

Bits flipped

Bit error rate

0.00%

SEU rate (measured)

0.0 / min

How it works

A Single-Event Upset (SEU) happens when one energetic ion or proton passes through a memory cell's silicon and leaves behind a trail of electron-hole pairs. If that trail deposits more charge than the cell's critical charge Q_crit, the stored bit flips — with no permanent damage to the hardware, just corrupted data. This is why spacecraft avionics run error-correcting memory and periodic "scrubbing".

Energy loss:     dE/dx = LET · ρ_Si   (Si density ≈ 2.33 g/cm³)
Deposited charge: Q ≈ 10.3 · LET · d_sens   [fC], d_sens in μm
Upset condition:  Q(track) > Q_crit  →  bit flips

The constant above is the standard silicon rule of thumb: an LET of 97 MeV·cm²/mg deposits about 1 pC per micron of path, from 3.6 eV needed per electron-hole pair. d_sens is the ~1-3 μm sensitive epitaxial depth of a real SRAM cell, so a steeper strike angle lengthens the path and deposits more charge for the same LET.

LET — how much energy the particle dumps per unit path length. Cosmic-ray heavy ions (iron, oxygen) reach LETs of tens to 100+ MeV·cm²/mg; solar protons are usually well below 10.
Q_crit — set by the memory's process node and supply voltage; smaller, lower-voltage transistors hold less charge and are easier to upset (a real driver behind "rad-hard" chip design).
Shielding — aluminum walls stop lower-energy particles outright, but the highest-LET galactic cosmic rays are energetic enough that thin shielding barely dents the flux reaching the die — shown here as an exponential fall-off with thickness.
At high LET the charge cloud is wide enough to spill into neighboring cells — a multi-cell upset, visible here as more than one cell flipping from a single strike.

Real-world relevance: SEUs are a routine hazard for every spacecraft, and are why flight computers use triple-modular redundancy, EDAC memory, and scheduled scrub cycles rather than trying to shield the problem away entirely.

Memory cell (0) Flipped bit (1) Incoming particle

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